- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366522 > AM29LV800BT-70SK (Advanced Micro Devices, Inc.) 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory PDF資料下載
參數(shù)資料
| 型號： | AM29LV800BT-70SK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 13/49頁 |
| 文件大?。?/td> | 859K |
| 代理商： | AM29LV800BT-70SK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Am29LV800B
11
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command reg-
ister itself does not occupy any addressable memory
location. The register is composed of latches that
store the commands, along with the address and data
information needed to execute the command. The
contents of the register serve as inputs to the internal
state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29LV800B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
2.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configu-
ration. If the BYTE# pin is set at logic ‘1’, the device
is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
IH
. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
Operation
CE#
L
L
V
CC
±
0.3 V
L
X
OE#
L
H
W E
#
H
L
R ESET#
H
H
V
CC
±
0.3 V
H
L
Addresses
( Note 1)
A
IN
A
IN
DQ0–
DQ7
D
OUT
D
IN
DQ8– DQ15
BY TE#
= V
I H
D
OUT
D
IN
BY TE#
= V
I L
Read
Write
DQ8–DQ14 = High-Z,
DQ15 = A-1
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
H
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
D
IN
X
X
Sector Unprotect (Note 2)
L
H
L
V
ID
D
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
D
IN
D
IN
High-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV800BT-70WBD | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70WBE | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70WBF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70WBK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| Am29LV800BB-90DP5C | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV800BT-90EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP 制造商:Analog Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP |
| AM29LV800DB-70EF | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 70ns 48-Pin TSOP |
| AM29LV800DB-90EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 90ns 48-Pin TSOP |
| AM29LV800DB-90ED | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 90ns 48-Pin TSOP |
| AM29LV800DB90EI | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。