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參數(shù)資料
| 型號： | AM29LV800BT-120WBE |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 6/49頁 |
| 文件大?。?/td> | 859K |
| 代理商： | AM29LV800BT-120WBE |
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Am29LV800B
GENERAL DESCRIPTION
The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-ball FBGA, 44-pin
SO, and 48-pin TSOP packages. The device is also
available in Known Good Die (KGD) form. For more
information, refer to publication number 21536. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This
device requires only a single, 3.0 volt V
CC
supply to
perform read, program, and erase operations. A stan-
dard EPROM programmer can also be used to program
and erase the device.
This device is manufactured using AMD’s 0.32 μm
process technology, and offers all the features and
benefits of the Am29LV800, which was manufactured
using 0.5 μm process technology. In addition, the
Am29LV800B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt pow er
supply
for both read and write functions. Internally
generated and regulated voltages are provided for
the program and erase operations.
The device is entirely command set compatible with
the
J EDEC single-pow er-supply Flash standard
.
Commands are written to the command register
using standard microprocessor write timings. Reg-
ister contents serve as input to an internal state-
machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase
operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Device programming occurs by executing the
program command sequence. This initiates the
Embedded Prog ram
algorithm—an internal algo-
rithm that automatically times the program pulse
widths and verifies proper cell margin. The
Unlock
Bypass
mode facilitates faster programming times
by requiring only two write cycles to program data
instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that auto-
matically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits
. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory
sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The
device is fully erased when shipped from the factory.
Hardw are data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardw are sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
feature enables the user to put
erase on hold for any period of time to read data
from, or program data to, any sector that is not
selected for erasure. True background erase can thus
be achieved.
The
hardw are RESET# pin
terminates any opera-
tion in progress and resets the internal state machine
to reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read the boot-up firmware from the Flash
memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode
.
The system can also place the device into the
s ta ndby m ode
. Power consumption is greatly
reduced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV800BT-120WBF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-120WBK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BB-70ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BB-70EE | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BB-70EF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV800BT-90EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP 制造商:Analog Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP |
| AM29LV800DB-70EF | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 70ns 48-Pin TSOP |
| AM29LV800DB-90EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 90ns 48-Pin TSOP |
| AM29LV800DB-90ED | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 90ns 48-Pin TSOP |
| AM29LV800DB90EI | 制造商:Advanced Micro Devices 功能描述: |
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