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參數(shù)資料
| 型號： | AM29LV800BB-90FD |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 20/49頁 |
| 文件大小： | 859K |
| 代理商： | AM29LV800BB-90FD |
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18
Am29LV800B
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is
not
required to provide
further controls or timings. The device automatically
provides internally generated program pulses and
verifies the programmed cell margin. Table 1 shows
the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that
a
hardw are reset
immediately terminates the pro-
gramming operation. The program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “ 0” back to a “ 1” .
Attempting to do so may
halt the operation and set DQ5 to “1”, or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than
using the standard program command sequence. The
unlock bypass command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command,
20h. The device then enters the unlock bypass mode.
A two-cycle unlock bypass program command
sequence is all that is required to program in this
mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second
cycle contains the program address and data. Addi-
tional data is programmed in the same manner. This
mode dispenses with the initial two unlock cycles
required in the standard program command
sequence, resulting in faster total programming time.
Table 1 shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t care for both cycles. The device then returns
to reading array data.
Figure 3 illustrates the algorithm for the program
operation. See the Erase/Program Operations table in
“AC Characteristics” for parameters, and to Figure 17
for timing diagrams.
Note:
See Table 1 for program command sequence.
Figure 3. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
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| AM29LV800BB-90FF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70EE | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70EF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV800BT-70EK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV800BT-120EI | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV800BT-120SCT | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV800BT-90EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP 制造商:Analog Devices 功能描述:NOR Flash, 512K x 16, 48 Pin, Plastic, TSSOP |
| AM29LV800DB-70EF | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 70ns 48-Pin TSOP |
| AM29LV800DB-90EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8/512K x 16 90ns 48-Pin TSOP |
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