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參數(shù)資料
| 型號： | AM29LV800BB-70FF |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 19/49頁 |
| 文件大?。?/td> | 859K |
| 代理商： | AM29LV800BB-70FF |
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Am29LV800B
17
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 1 for
command definitions). In addition, the following
hardware data protection measures prevent acci-
dental erasure or programming, which might other-
wise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or
from system noise.
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not
accept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until V
CC
is greater than V
LKO
. The system must
provide the proper signals to the control pins to
prevent unintentional writes when V
CC
is greater than
V
LKO
.
W rite Pulse “ Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical I nhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write
cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Pow er-Up W rite I nhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automat-
ically reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register
command sequences. Writing
incorrect
address
and data values
or writing them in the
improper
sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched
on the rising edge of WE# or CE#, whichever
happens first. Refer to the appropriate timing dia-
grams in the “AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in
the Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must
issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more infor-
mation. The Read Operations table provides the read
parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to
reading array data. Once erasure begins, however,
the device ignores reset commands until the opera-
tion is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase opera-
tion, writing the reset command returns the device to
reading array data (also applies during Erase Sus-
pend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices
codes, and determine whether or not a sector is pro-
tected. Table 1 shows the address and data require-
ments. This method is an alternative to that shown in
Table 4, which is intended for PROM programmers
and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
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| AM29LV800BB-70FK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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| AM29LV800BB-70SK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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