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參數(shù)資料
| 型號： | AM29LV640MU120RWHI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) MirrorBita?? 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/Oa?? Control |
| 中文描述： | 4M X 16 FLASH 3V PROM, 120 ns, PBGA63 |
| 封裝： | 12 X 11 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數(shù)： | 33/59頁 |
| 文件大?。?/td> | 699K |
| 代理商： | AM29LV640MU120RWHI |
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February1,2007 25301C5
Am29LV640MU
31
D A T A S H E E T
Command Definitions
Table 10.
Command Definitions
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
4.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits higher than A11 and
data bits higher than DQ7 are don’t care.
Unless otherwise noted, address bits A21–A11 are don’t cares.
No unlock or command cycles required when device is in read
mode.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care, except for RD, PD and
WC. See the
Autoselect Command Sequence
section for more
information.
The device ID must be read in three cycles.
5.
6.
7.
8.
9.
10. The data is 98h for factory locked and 18h for not factory locked.
11. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21,
including "Program Buffer to Flash" command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
17. The Erase Resume command is valid only during the Erase
Suspend mode.
18. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command Sequence (Notes)
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID (Note 9)
Secured Silicon Sector Factory
Protect (Note 10)
C
1
1
4
6
Bus Cycles (Notes 1–4)
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
A
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
Write to Buffer (Note 12)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
X0E
2213
X0F
2201
4
555
AA
2AA
55
555
90
X03
(Note 10)
Sector Group Protect Verify
(Note 11)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
SA
00
PD
WC
PA
PD
WBL
PD
2AA
2AA
PA
XXX
2AA
2AA
55
55
PD
00
55
55
555
555
F0
20
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
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