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參數資料

型號：	Am29LV640DH90RPCIN
廠商：	Advanced Micro Devices, Inc.
英文描述：	64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI Control
中文描述：	64兆位（4個M x 16位），3.0伏的CMOS只均勻部門閃光控制記憶與VersatileI
文件頁數：	34/57頁
文件大?。?/td>	1467K
代理商：	AM29LV640DH90RPCIN

September 20, 2002

Am29LV640D/Am29LV641D

3

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA/fBGA Packages ......... 8

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11

Table 1. Device Bus Operations .....................................................11

(V

IO) Control ..................................................... 11

Requirements for Reading Array Data ................................... 11

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation ......................................................12

Autoselect Functions .......................................................................12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ........................................................... 12

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 13

Table 2. Sector Address Table ........................................................13

Autoselect Mode ..................................................................... 17

Table 3. Autoselect Codes, (High Voltage Method) .......................17

Sector Group Protection and Unprotection ............................. 18

Table 4. Sector Group Protection/Unprotection Address Table .....18

Write Protect (WP#) ................................................................ 19

Temporary Sector Group Unprotect ....................................... 19

Figure 1. Temporary Sector Group Unprotect Operation................ 19

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20

SecSi (Secured Silicon) Sector Flash Memory Region .......... 21

Table 5. SecSi Sector Contents ......................................................21

Hardware Data Protection ...................................................... 21

Low VCC Write Inhibit .....................................................................21

Write Pulse “Glitch” Protection ........................................................22

Logical Inhibit ..................................................................................22

Power-Up Write Inhibit ....................................................................22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 6. CFI Query Identification String .......................................... 22

System Interface String................................................................... 23

Table 8. Device Geometry Definition .............................................. 23

Table 9. Primary Vendor-Specific Extended Query ........................ 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . 24

Reading Array Data ................................................................ 24

Reset Command ..................................................................... 25

Autoselect Command Sequence ............................................ 25

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25

Word Program Command Sequence ..................................... 25

Unlock Bypass Command Sequence ..............................................26

Figure 3. Program Operation .......................................................... 26

Chip Erase Command Sequence ........................................... 26

Sector Erase Command Sequence ........................................ 27

Erase Suspend/Erase Resume Commands ........................... 27

Figure 4. Erase Operation............................................................... 28

Command Definitions ............................................................. 29

Command Definitions...................................................................... 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 5. Data# Polling Algorithm ................................................... 30

RY/BY#: Ready/Busy# ............................................................ 31

DQ6: Toggle Bit I .................................................................... 31

Figure 6. Toggle Bit Algorithm........................................................ 31

DQ2: Toggle Bit II ................................................................... 32

Reading Toggle Bits DQ6/DQ2 ............................................... 32

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer ....................................................... 32

Table 11. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform ..................... 34

Figure 8. Maximum Positive Overshoot Waveform....................... 34

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

CC1 Current vs. Time (Showing

Active and Automatic Sleep Currents) ........................................... 36

Figure 10. Typical I

CC1 vs. Frequency ............................................ 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. Test Setup.................................................................... 37

Table 12. Test Specifications ......................................................... 37

Key to Switching Waveforms. . . . . . . . . . . . . . . . 37

Figure 12. Input Waveforms and

Measurement Levels...................................................................... 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

Read-Only Operations ........................................................... 38

Figure 13. Read Operation Timings ............................................... 38

Hardware Reset (RESET#) .................................................... 39

Figure 14. Reset Timings ............................................................... 39

Erase and Program Operations .............................................. 40

Figure 15. Program Operation Timings.......................................... 41

Figure 16. Accelerated Program Timing Diagram .......................... 41

Figure 17. Chip/Sector Erase Operation Timings .......................... 42

Figure 18. Data# Polling Timings

(During Embedded Algorithms)...................................................... 43

Figure 19. Toggle Bit Timings

(During Embedded Algorithms)...................................................... 44

Figure 20. DQ2 vs. DQ6................................................................. 44

Temporary Sector Unprotect .................................................. 45

Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 45

Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 46

Alternate CE# Controlled Erase and Program Operations ..... 47

Figure 23. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 48

Erase And Programming Performance . . . . . . . 49

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50

SSO056—56-Pin Shrink Small Outline Package (SSOP) ...... 50

FBE063—63-Ball Fine-Pitch Ball Grid Array

(FBGA) 12 x 11 mm package ................................................. 51

LAA064—64-Ball Fortified Ball Grid Array

(FBGA) 13 x 11 mm package ................................................. 52

TS 048—48-Pin Standard TSOP ............................................ 53

TSR048—48-Pin Reverse TSOP ........................................... 54

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55

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