參數(shù)資料
型號(hào)： AM29LV256MH123PGI
廠商： ADVANCED MICRO DEVICES INC
元件分類： PROM
英文描述： 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
中文描述： 16M X 16 FLASH 3V PROM, 120 ns, PBGA64
封裝： 18 X 12 MM, 1 MM PITCH, FORTIFIED, BGA-64
文件頁數(shù)： 40/69頁
文件大小： 546K
代理商： AM29LV256MH123PGI
38
Am29LV256M
December 16, 2005
D A T A S H E E T
Figure 6.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
11
and
12
show the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the
Write Operation Status
section for infor-
mation on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a
hardware reset
im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 10
illustrates the algorithm for the erase opera-
tion. Refer to the
Erase and Program Operations
ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command.
Table 12
shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does
not
require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 μs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
μs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written.
Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode.
The system must re-
write the command sequence and any additional ad-
dresses and commands.
Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an
erase operation in is progress.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Done
reading
No
Yes
Write address/data
XXXh/3030h
Device reverts to
operation prior to
Program Suspend
Write address/data
XXXh/B0B0h
Wait 15 ms
相關(guān)PDF資料
PDF描述
AM29LV256MH123REF 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
AM29LV256MH123RPGF 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
AM29LV256MH30EF 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
AM29LV256MH30EI 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
AM29LV256MH30FF 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29LV256MH123RPGI 制造商:Advanced Micro Devices 功能描述:
AM29LV256MH94REI 制造商:Spansion 功能描述:256M (32MX8/16MX16) 3V REG, MIRRORBIT, TSOP56, IND - Trays
AM29LV320DB120EI 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin TSOP
AM29LV320DB120WMI 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin FBGA
AM29LV320DB90EC 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP
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