參數(shù)資料
型號: AM29LV256MH113FI
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: 256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
中文描述: 16M X 16 FLASH 3V PROM, 110 ns, PDSO56
封裝: REVERSE, MO-142B, TSOP-56
文件頁數(shù): 42/69頁
文件大?。?/td> 546K
代理商: AM29LV256MH113FI
40
Am29LV256M
December 16, 2005
D A T A S H E E T
Command Definitions
Table 11.
Command Definitions (x16 Mode, BYTE# = V
IH
)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A23–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD, PD and WC.
Unless otherwise noted, address bits A23–A11 are don’t cares.
No unlock or command cycles required when device is in read
mode.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the
Autoselect
Command Sequence
section for more information.
The device ID must be read in three cycles.
10. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
4.
5.
6.
7.
8.
9.
lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.
12. The data is 00h for an unprotected sector and 01h for a protected
sector.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
17. The Erase Resume command is valid only during the Erase
Suspend mode.
18. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
C
Bus Cycles (Notes 2–5)
Third
Addr
Data
First
Second
Addr
Fourth
Fifth
Sixth
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Data
Addr
Data
Addr
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID (Note 9)
SecSi
TM
Sector Factory Protect
(Note 10)
1
1
4
4
A
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
X0E
2212
X0F
2201
4
555
AA
2AA
55
555
90
X03
(Note 10)
Sector Group Protect Verify
(Note 12)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
SA
00
PD
WC
PA
PD
WBL
PD
2AA
2AA
PA
XXX
2AA
2AA
55
55
PD
00
55
55
555
555
F0
20
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
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