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參數(shù)資料
| 型號： | AM29LV200BT-70WAC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 128K X 16 FLASH 3V PROM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 12/46頁 |
| 文件大?。?/td> | 716K |
| 代理商： | AM29LV200BT-70WAC |
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10
Am29LV200B
21521D6 October 10, 2006
DA T A S HE E T
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Am29LV200B Command
Definitions” section has details on erasing a sector or
the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
I
CC2
in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
±
0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
±
0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC4
in the DC Char-
acteristics table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RESET#
pin is driven low for at least a period of t
RP
, the device
immediately terminates
any operation in progress,
tristates all output pins, and ignores all read/write com-
mands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array
data. The operation that was interrupted should be rein-
itiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V
SS
±0.3 V, the device draws
CMOS standby current (I
CC4
). If RESET# is held at V
IL
but not within V
SS
±0.3 V, the standby current will be
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
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