
22
Am29LV200B
21521D6  October 10, 2006
  DA T A  S HE E T
The remaining scenario is that the system initially 
determines that the toggle bit is toggling and DQ5 has 
not gone high. The system may continue to monitor the 
toggle bit and DQ5 through successive read cycles, 
determining the status as described in the previous 
paragraph. Alternatively, it may choose to perform 
other system tasks. In this case, the system must start 
at the beginning of the algorithm when it returns to 
determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has 
exceeded a specified internal pulse count limit. Under 
these conditions DQ5 produces a “1.” This is a failure 
condition that indicates the program or erase cycle was 
not successfully completed. 
The DQ5 failure condition may appear if the system 
tries to program a “1” to a location that is previously pro-
grammed to “0.” 
Only an erase operation can change 
a “0” back to a “1.”
 Under this condition, the device 
halts the operation, and when the operation has 
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the 
reset command to return the device to reading array 
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the 
system may read DQ3 to determine whether or not an 
erase operation has begun. (The sector erase timer 
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches 
from “0” to “1.” If the time between additional sector 
erase commands from the system can be assumed to 
be less than 50 μs, the system need not monitor DQ3. 
See also the “Sector Erase Command Sequence” 
section.
After the sector erase command sequence is written, 
the system should read the status on DQ7 (Data# 
Polling) or DQ6 (Toggle Bit I) to ensure the device has 
accepted the command sequence, and then read DQ3. 
If DQ3 is “1”, the internally controlled erase cycle has 
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete. 
If DQ3 is “0”, the device will accept additional sector 
erase commands. To ensure the command has been 
accepted, the system software should check the status 
of DQ3 prior to and following each subsequent sector 
erase command. If DQ3 is high on the second status 
check, the last command might not have been 
accepted. Table 6 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
 = Toggle
No
Program/Erase
Operation Not 
Complete, Write 
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
 = Toggle
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is 
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 
changes to “1” . See text.
Figure 6. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)