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    參數(shù)資料
    型號(hào): AM29LV160BB80SE
    廠商: ADVANCED MICRO DEVICES INC
    元件分類: PROM
    英文描述: 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
    中文描述: 2M X 8 FLASH 3V PROM, 80 ns, PDSO44
    封裝: SOP-44
    文件頁(yè)數(shù): 26/48頁(yè)
    文件大小: 695K
    代理商: AM29LV160BB80SE
    Am29LV160B
    25
    RY/BY#: Ready/Busy#
    The RY/BY# is a dedicated, open-drain output pin that
    indicates whether an Embedded Algorithm is in
    progress or complete. The RY/BY# status is valid after
    the rising edge of the final WE# pulse in the command
    sequence. Since RY/BY# is an open-drain output,
    several RY/BY# pins can be tied together in parallel
    with a pull-up resistor to V
    CC
    . (The RY/BY# pin is not
    available on the 44-pin SO package.)
    If the output is low (Busy), the device is actively erasing
    or programming. (This includes programming in the
    Erase Suspend mode.) If the output is high (Ready),
    the device is ready to read array data (including during
    the Erase Suspend mode), or is in the standby mode.
    Table 10 shows the outputs for RY/BY#. Figures 13, 14,
    17 and 18 shows RY/BY# for read, reset, program, and
    erase operations, respectively.
    DQ6: Toggle Bit I
    Toggle Bit I on DQ6 indicates whether an Embedded
    Program or Erase algorithm is in progress or complete,
    or whether the device has entered the Erase Suspend
    mode. Toggle Bit I may be read at any address, and is
    valid after the rising edge of the final WE# pulse in the
    command sequence (prior to the program or erase
    operation), and during the sector erase time-out.
    During an Embedded Program or Erase algorithm
    operation, successive read cycles to any address
    cause DQ6 to toggle. (The system may use either OE#
    or CE# to control the read cycles.) When the operation
    is complete, DQ6 stops toggling.
    After an erase command sequence is written, if all
    sectors selected for erasing are protected, DQ6 toggles
    for approximately 100 μs, then returns to reading array
    data. If not all selected sectors are protected, the
    Embedded Erase algorithm erases the unprotected
    sectors, and ignores the selected sectors that are pro-
    tected.
    The system can use DQ6 and DQ2 together to deter-
    mine whether a sector is actively erasing or is erase-
    suspended. When the device is actively erasing (that is,
    the Embedded Erase algorithm is in progress), DQ6
    toggles. When the device enters the Erase Suspend
    mode, DQ6 stops toggling. However, the system must
    also use DQ2 to determine which sectors are erasing
    or erase-suspended. Alternatively, the system can use
    DQ7 (see the subsection on “DQ7: Data# Polling”).
    If a program address falls within a protected sector,
    DQ6 toggles for approximately 1 μs after the program
    command sequence is written, then returns to reading
    array data.
    DQ6 also toggles during the erase-suspend-program
    mode, and stops toggling once the Embedded
    Program algorithm is complete.
    Table 10 shows the outputs for Toggle Bit I on DQ6.
    Figure 6 shows the toggle bit algorithm in flowchart
    form, and the section “Reading Toggle Bits DQ6/DQ2”
    explains the algorithm. Figure 20 in the “AC Character-
    istics” section shows the toggle bit timing diagrams.
    Figure 21 shows the differences between DQ2 and
    DQ6 in graphical form. See also the subsection on
    “DQ2: Toggle Bit II”.
    DQ2: Toggle Bit II
    The “Toggle Bit II” on DQ2, when used with DQ6, indi-
    cates whether a particular sector is actively erasing
    (that is, the Embedded Erase algorithm is in progress),
    or whether that sector is erase-suspended. Toggle Bit
    II is valid after the rising edge of the final WE# pulse in
    the command sequence.
    DQ2 toggles when the system reads at addresses
    within those sectors that have been selected for era-
    sure. (The system may use either OE# or CE# to
    control the read cycles.) But DQ2 cannot distinguish
    whether the sector is actively erasing or is erase-sus-
    pended. DQ6, by comparison, indicates whether the
    device is actively erasing, or is in Erase Suspend, but
    cannot distinguish which sectors are selected for era-
    sure. Thus, both status bits are required for sector and
    mode information. Refer to Table 10 to compare
    outputs for DQ2 and DQ6.
    Figure 6 shows the toggle bit algorithm in flowchart
    form, and the section “Reading Toggle Bits DQ6/DQ2”
    explains the algorithm. See also the DQ6: Toggle Bit I
    subsection. Figure 20 shows the toggle bit timing dia-
    gram. Figure 21 shows the differences between DQ2
    and DQ6 in graphical form.
    Reading Toggle Bits DQ6/DQ2
    Refer to Figure 6 for the following discussion. When-
    ever the system initially begins reading toggle bit sta-
    tus, it must read DQ7–DQ0 at least twice in a row to
    determine whether a toggle bit is toggling. Typically,
    the system would note and store the value of the tog-
    gle bit after the first read. After the second read, the
    system would compare the new value of the toggle bit
    with the first. If the toggle bit is not toggling, the device
    has completed the program or erase operation. The
    system can read array data on DQ7–DQ0 on the fol-
    lowing read cycle.
    However, if after the initial two read cycles, the system
    determines that the toggle bit is still toggling, the
    system also should note whether the value of DQ5 is
    high (see the section on DQ5). If it is, the system
    should then determine again whether the toggle bit is
    toggling, since the toggle bit may have stopped tog-
    gling just as DQ5 went high. If the toggle bit is no longer
    toggling, the device has successfully completed the
    program or erase operation. If it is still toggling, the
    device did not complete the operation successfully, and
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