參數(shù)資料
型號(hào)： AM29LV128ML103EI
廠商： ADVANCED MICRO DEVICES INC
元件分類： PROM
英文描述： 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
中文描述： 8M X 16 FLASH 3V PROM, 100 ns, PDSO56
封裝： MO-142B, TSOP-56
文件頁數(shù)： 4/65頁
文件大?。?/td> 1222K
代理商： AM29LV128ML103EI
2
Am29LV128MH/L
September 9, 2003
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV128MH/L is a 128 Mbit, 3.0 volt single
power supply flash memory devices organized as
8,388,608 words or 16,777,216 bytes. The device has
a 16-bit wide data bus that can also function as an
8-bit wide data bus by using the BYTE# input. The de-
vice can be programmed either in the host system or
in standard EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
56-pin TSOP, 64-ball Fortified BGA. Each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(
WP#/
ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard
.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
→
→
相關(guān)PDF資料
PDF描述
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