參數(shù)資料
型號(hào)： Am29LV116BT-80RFCB
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述： 16兆位（2米× 8位）的CMOS 3.0伏，只引導(dǎo)扇區(qū)閃存
文件頁(yè)數(shù)： 14/40頁(yè)
文件大小： 544K
代理商： AM29LV116BT-80RFCB
Am29LV116B
14
P R E L IM IN A R Y
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array
data. The system can read CFI information at the
addresses given in Tables 5–8. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represent-
ative for copies of these documents.
Table 5.
CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table (00h = none exists)
Table 6.
System Interface String
Addresses
Data
Description
1Bh
27h
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
00h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
00h
V
PP
Max. voltage (00h = no V
PP
pin present)
Typical timeout per single byte/word write 2
N
μs
1Fh
04h
20h
00h
Typical timeout for Min. size buffer write 2
N
μs (00h = not supported)
21h
0Ah
Typical timeout per individual block erase 2
N
ms
22h
00h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
05h
Max. timeout for byte/word write 2
N
times typical
24h
00h
Max. timeout for buffer write 2
N
times typical
25h
04h
Max. timeout per individual block erase 2
N
times typical
26h
00h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
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