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參數(shù)資料
| 型號： | AM29LV033MU |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | LM3622 Lithium-Ion Battery Charger Controller; Package: SOIC NARROW; No of Pins: 8; Qty per Container: 2500; Container: Reel |
| 中文描述： | 32兆位（4個M × 8位）的MirrorBit 3.0伏特，只有統(tǒng)一閃存部門與VersatileI / O控制 |
| 文件頁數(shù)： | 12/56頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | AM29LV033MU |
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12
Am29LV033MU
November 11, 2002
A D V A N C E I N F O R M A T I O N
Refer to the
DC Characteristics
table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current. If RESET# is held at V
IL
but not within V
SS
±0.3 V, the standby current will be
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY
(not during Embedded
Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the
AC Characteristics
tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
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| AM29LV033MUU90WCI | 32 Megabit (4 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control |
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| AM29LV033MUU112RFI | 32 Megabit (4 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control |
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