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參數(shù)資料
| 型號： | AM29LV033C-90EF |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory |
| 中文描述： | 32兆位（4個M × 8位）的CMOS 3.0伏特，只有統(tǒng)一部門閃存 |
| 文件頁數(shù)： | 12/49頁 |
| 文件大?。?/td> | 693K |
| 代理商： | AM29LV033C-90EF |
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10
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 2, on page 13
indi-
cates the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. The “Command Defini-
tions” section contains details for erasing a sector or
the entire chip, or suspending/resuming the erase op-
eration.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the
“Autoselect Mode” on page 15
and
“Autoselect Command Sequence” on page 21
sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The
“AC
Characteristics” on page 34
section contains timing
specification tables and timing diagrams for write oper-
ations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the ACC pin. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
If the system asserts V
HH
on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system then
uses a two-cycle program command sequence as re-
quired by the Unlock Bypass mode. Removing V
HH
from the ACC pin returns the device to normal opera-
tion. Note that the ACC pin must not be at V
HH
for op-
erations other than accelerated programming, or
device damage may result.
Program and Erase Operation Status
During an erase or program operation, the system
checks the status of the operation by reading the sta-
tus bits on DQ7–DQ0. Standard read cycle timings
and I
CC
read specifications apply. Refer to
“Write Op-
eration Status” on page 26
for more information, and
to
“AC Characteristics” on page 34
for timing dia-
grams.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
±
0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
±
0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (t
CE
) for read access when the de-
vice is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”
.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
ACC
+ 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. I
CC4
in the DC Characteristics table
represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would also reset the Flash mem-
ory, enabling the system to read the boot-up firmware
from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
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