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參數(shù)資料
| 型號(hào)： | AM29F400BT-75DPC1 |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| 中文描述： | 512K X 8 FLASH 5V PROM, 70 ns, UUC43 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 139K |
| 代理商： | AM29F400BT-75DPC1 |
2
Am29F400B Known Good Die
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29F400B in Known Good Die (KGD) form is a
4 Mbit, 5.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same relia-
bility and quality as AMD products in packaged form.
Am29F400B Features
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
is designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. A 12.0 V V
PP
is
not required for write or erase operations. The device
can also be programmed in standard EPROM pro-
grammers.
This device is manufactured using AMD’s 0.35 μm
process technology, and offers all the features and ben-
efits of the Am29F400, which was manufactured using
0.5 μm process technology.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits
. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby mode
.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F400B data sheet, document
number 21505, for full electrical specifications on the
Am29F400B in KGD form.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F400BB-75DPC1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| Am29F400BT-75DPE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| Am29F400BB-75DPE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| AM29F400BT-75DPE1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| AM29F400BB-75DPE1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F400BT-90EC | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8/256K x 16 90ns 48-Pin TSOP |
| AM29F400BT-90ED | 制造商:Spansion 功能描述:FLASH TOP BLOCK 4MB SMD 29F400 |
| AM29F400BT-90EF | 功能描述:閃存 4M (512KX8/256Kx16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AM29F400BT-90EI\T | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8/256K x 16 90ns 48-Pin TSOP T/R |
| AM29F400BT-90SE\T | 制造商:Spansion 功能描述:4 MEGABIT (512 K X 8-BIT/256 K X 16-BIT) CMOS 5.0 VOLT-ONLY BOOT SECTOR FLASH MEMORY |
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