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參數資料
| 型號： | AM29F100T-70EEB |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 1 Megabit (128 K x 8-bit/64 K x 16-bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 128K X 8 FLASH 5V PROM, 70 ns, PDSO48 |
| 封裝： | TSOP-48 |
| 文件頁數： | 2/8頁 |
| 文件大?。?/td> | 57K |
| 代理商： | AM29F100T-70EEB |
2
Am29F100 Known Good Die
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29F100 in Known Good Die (KGD) form is a 1
Mbit, 5.0 Volt-only Flash memory. AMD defines KGD as
standard product in die form, tested for functionality
and speed. AMD KGD products have the same reli-
ability and quality as AMD products in packaged form.
Am29F100 Features
The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes or 65,536 words. Word-
wide data appears on DQ0-DQ15; byte-wide data on
DQ0-DQ7. The device is designed to be programmed
in-system with the standard system 5.0 Volt V
CC
sup-
ply. A 12.0 volt V
PP
is not required for program or erase
operations. The device can also be programmed or
erased in standard EPROM programmers.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output en-
able (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the pro-
gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits
. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
Erase Suspend
feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The
hardware data protection
measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The
hardware sector pro-
tection
feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is implemented using standard EPROM program-
mers. The
temporary sector unprotect
feature allows
in-system changes to protected sectors.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby mode
.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F100 data sheet, document number
18926, for full electrical specifications on the
Am29F100.
相關PDF資料 |
PDF描述 |
|---|---|
| AM29F100T-70EI | 1 Megabit (128 K x 8-bit/64 K x 16-bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F100 | 1 Megabit (128 K x 8-bit/64 K x 16-bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F100-1 | 1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| AM29F160DB90 | 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F160D | 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AM29F160DB-120EC | 制造商:Spansion 功能描述:16M (2MX8/1MX16) 5V, BOOT BLOCK, BOT, TSOP48, COM - Trays |
| AM29F160DB-120EI | 制造商:Spansion 功能描述:16M (2MX8/1MX16) 5V, BOOT BLOCK, BOT, TSOP48, IND - Trays |
| AM29F160DB-70ED | 制造商:Spansion 功能描述: |
| AM29F160DB-70EF | 功能描述:閃存 16Mb 70ns 5v Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AM29F160DB-70EFT | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 16Mbit 2M/1M x 8bit/16bit 70ns 48-Pin TSOP T/R |
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