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    參數(shù)資料
    

    


    


    
型號(hào)：
AM29F080B-90SD

    

    
廠商：
Advanced Micro Devices, Inc.

    

    
英文描述：
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    
中文描述：
8兆位（1米× 8位）的CMOS 5.0伏只，統(tǒng)一部門(mén)快閃記憶體

    

    
文件頁(yè)數(shù)：
16/39頁(yè)

    

    
文件大?。?/td>
517K

    

    
代理商：
AM29F080B-90SD


    

    

    

	
    
    
    

    
    
	
    14
    Am29F080B
    21503G5 November1,2006
    D AT A  S H E E T
    quence should be reinitiated once the device has
    returned to reading array data, to ensure data integrity.
    The system can determine the status of the erase
    operation by using DQ7, DQ6, DQ2, or RY/BY#. See
    “Write Operation Status” for information on these
    status bits. When the Embedded Erase algorithm is
    complete, the device returns to reading array data
    and addresses are no longer latched. 
    Figure 3 illustrates the algorithm for the erase opera-
    tion. See the Erase/Program Operations tables in “AC
    Characteristics” for parameters, and to the Chip/Sector
    Erase Operation Timings for timing waveforms.
    Sector Erase Command Sequence
    Sector erase is a six bus cycle operation. The sector
    erase command sequence is initiated by writing two un-
    lock cycles, followed by a set-up command. Two addi-
    tional unlock write cycles are then followed by the
    address of the sector to be erased, and the sector
    erase command. The Command Definitions table
    shows the address and data requirements for the sec-
    tor erase command sequence.
    The device does 
    not
     require the system to preprogram
    the memory prior to erase. The Embedded Erase algo-
    rithm automatically programs and verifies the sector for
    an all zero data pattern prior to electrical erase. The
    system is not required to provide any controls or tim-
    ings during these operations. 
    After the command sequence is written, a sector erase
    time-out of 50 μs begins. During the time-out period,
    additional sector addresses and sector erase com-
    mands may be written. Loading the sector erase buffer
    may be done in any sequence, and the number of sec-
    tors may be from one sector to all sectors. The time be-
    tween these additional cycles must be less than 50 
    μ
    s,
    otherwise the last address and command might not be
    accepted, and erasure may begin. It is recommended
    that processor interrupts be disabled during this time to
    ensure all commands are accepted. The interrupts can
    be re-enabled after the last Sector Erase command is
    written. If the time between additional sector erase
    commands can be assumed to be less than 50 μs, the
    system need not monitor DQ3. 
    Any command other
    than Sector Erase or Erase Suspend during the
    time-out period resets the device to reading array
    data.
     The system must rewrite the command sequence
    and any additional sector addresses and commands.
    The system can monitor DQ3 to determine if the sector
    erase timer has timed out. (See the “DQ3: Sector Erase
    Timer” section.) The time-out begins from the rising
    edge of the final WE# pulse in the command sequence.
    Once the sector erase operation has begun, only the
    Erase Suspend command is valid. All other commands
    are ignored. Note that a 
    hardware reset
     during the
    sector erase operation immediately terminates the op-
    eration. The Sector Erase command sequence should
    be reinitiated once the device has returned to reading
    array data, to ensure data integrity.
    When the Embedded Erase algorithm is complete, the
    device returns to reading array data and addresses are
    no longer latched. The system can determine the sta-
    tus of the erase operation by using DQ7, DQ6, DQ2, or
    RY/BY#. Refer to “Write Operation Status” for informa-
    tion on these status bits.
    Figure 3 illustrates the algorithm for the erase opera-
    tion. Refer to the Erase/Program Operations tables in
    the “AC Characteristics” section for parameters, and to
    the Sector Erase Operations Timing diagram for timing
    waveforms.
    Erase Suspend/Erase Resume Commands
    The Erase Suspend command allows the system to in-
    terrupt a sector erase operation and then read data
    from, or program data to, any sector not selected for
    erasure. This command is valid only during the sector
    erase operation, including the 50 μs time-out period
    during the sector erase command sequence. The
    Erase Suspend command is ignored if written during
    the chip erase operation or Embedded Program algo-
    rithm. Writing the Erase Suspend command during the
    Sector Erase time-out immediately terminates the
    time-out period and suspends the erase operation. Ad-
    dresses are “don’t-cares” when writing the Erase Sus-
    pend command.
    When the Erase Suspend command is written during a
    sector erase operation, the device requires a maximum
    of 20 
    μ
    s to suspend the erase operation. However,
    when the Erase Suspend command is written during
    the sector erase time-out, the device immediately ter-
    minates the time-out period and suspends the erase
    operation.
    After the erase operation has been suspended, the
    system can read array data from or program data to
    any sector not selected for erasure. (The device “erase
    suspends” all sectors selected for erasure.) Normal
    read and write timings and command definitions apply.
    Reading at any address within erase-suspended sec-
    tors produces status data on DQ7–DQ0. The system
    can use DQ7, or DQ6 and DQ2 together, to determine
    if a sector is actively erasing or is erase-suspended.
    See “Write Operation Status” for information on these
    status bits.
    After an erase-suspended program operation is com-
    plete, the system can once again read array data within
    non-suspended sectors. The system can determine
    the status of the program operation using the DQ7 or
    DQ6 status bits, just as in the standard program oper-
    ation. See “Write Operation Status” for more informa-
    tion.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
AM29F080B-90SF
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    
AM29F080B-90SK
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    
AM29F080B-120EF
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    
AM29F080B-120EK
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    
AM29F080B-120SD
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
AM29F080B-90SD
 制造商:Spansion 功能描述:FLASH 8MB SMD 29F080 SOIC44

    

    
AM29F080B-90SF
 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:IC, FLASH MEM, 8MBIT, 90NS, 44-SOIC,  Memory Type:Flash - NOR,  Memory Size:8Mbit,

    

    
AM29F080B-90SI
 制造商:Advanced Micro Devices 功能描述:

    

    
AM29F100B120EC
 制造商:AMD 功能描述:*

    

    
AM29F100B-120EC
 制造商:Advanced Micro Devices 功能描述:

    

    
    
    
    
	
    	
    
    
     
     
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