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      參數(shù)資料
      型號(hào): AM29F080B-55EE
      廠(chǎng)商: Advanced Micro Devices, Inc.
      英文描述: 8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
      中文描述: 8兆位(1米× 8位)的CMOS 5.0伏只,統(tǒng)一部門(mén)快閃記憶體
      文件頁(yè)數(shù): 10/39頁(yè)
      文件大?。?/td> 517K
      代理商: AM29F080B-55EE
      8
      Am29F080B
      21503G5 November1,2006
      D AT A S H E E T
      DEVICE BUS OPERATIONS
      This section describes the requirements and use of the
      device bus operations, which are initiated through the
      internal command register. The command register it-
      self does not occupy any addressable memory loca-
      tion. The register is composed of latches that store the
      commands, along with the address and data informa-
      tion needed to execute the command. The contents of
      the register serve as inputs to the internal state ma-
      chine. The state machine outputs dictate the function of
      the device. The appropriate device bus operations
      table lists the inputs and control levels required, and the
      resulting output. The following subsections describe
      each of these operations in further detail.
      Table 1.
      Am29F080B Device Bus Operations
      Legend:
      L = Logic Low = V
      IL
      , H = Logic High = V
      IH
      , D
      OUT
      = Data Out, D
      IN
      = Data In, A
      IN
      = Address In, X = Don’t Care. See DC Charac-
      teristics for voltage levels.
      Note:
      See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
      Requirements for Reading Array Data
      To read array data from the outputs, the system must
      drive the CE# and OE# pins to V
      IL
      . CE# is the power
      control and selects the device. OE# is the output control
      and gates array data to the output pins. WE# should re-
      main at V
      IH
      .
      The internal state machine is set for reading array
      data upon device power-up, or after a hardware reset.
      This ensures that no spurious alteration of the mem-
      ory content occurs during the power transition. No
      command is necessary in this mode to obtain array
      data. Standard microprocessor read cycles that as-
      sert valid addresses on the device address inputs
      produce valid data on the device data outputs. The
      device remains enabled for read access until the
      command register contents are altered.
      See “Reading Array Data” for more information. Refer
      to the AC Read Operations table for timing specifica-
      tions and to the Read Operations Timings diagram for
      the timing waveforms. I
      CC1
      in the DC Characteristics
      table represents the active current specification for
      reading array data.
      Writing Commands/Command Sequences
      To write a command or command sequence (which in-
      cludes programming data to the device and erasing
      sectors of memory), the system must drive WE# and
      CE# to V
      IL
      , and OE# to V
      IH
      .
      An erase operation can erase one sector, multiple sec-
      tors, or the entire device. The Sector Address Tables in-
      dicate the address space that each sector occupies. A
      “sector address” consists of the address bits required
      to uniquely select a sector. See the Command Defini-
      tions section for details on erasing a sector or the entire
      chip, or suspending/resuming the erase operation.
      After the system writes the autoselect command se-
      quence, the device enters the autoselect mode. The
      system can then read autoselect codes from the inter-
      nal register (which is separate from the memory array)
      on DQ7–DQ0. Standard read cycle timings apply in this
      mode. Refer to the Autoselect Mode and Autoselect
      Command Sequence sections for more information.
      I
      CC2
      in the DC Characteristics table represents the ac-
      tive current specification for the write mode. The “AC
      Characteristics” section contains timing specification
      tables and timing diagrams for write operations.
      Program and Erase Operation Status
      During an erase or program operation, the system may
      check the status of the operation by reading the status
      bits on DQ7–DQ0. Standard read cycle timings and I
      CC
      read specifications apply. Refer to “Write Operation
      Operation
      CE#
      OE#
      WE#
      RESET#
      A0–A19
      DQ0
      DQ7
      Read
      L
      L
      X
      H
      A
      IN
      D
      OUT
      Write
      L
      H
      L
      H
      A
      IN
      D
      IN
      TTL Standby
      H
      X
      X
      H
      X
      HIGH Z
      CMOS Standby
      V
      CC
      ±
      0.3 V
      X
      X
      V
      CC
      ±
      0.3 V
      X
      HIGH Z
      Output Disable
      L
      H
      H
      H
      X
      HIGH Z
      Hardware Reset
      X
      X
      X
      V
      IL
      X
      HIGH Z
      Temporary Sector Group Unprotect (See Note)
      X
      X
      X
      V
      ID
      A
      IN
      X
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