參數(shù)資料
型號(hào)： AM29F032B-90EC
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： PROM
英文描述： 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
中文描述： 4M X 8 FLASH 5V PROM, 90 ns, PDSO40
封裝： MO-142CD, TSOP-40
文件頁(yè)數(shù)： 14/39頁(yè)
文件大?。?/td> 937K
代理商： AM29F032B-90EC
Am29F032B
13
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection.
In addition, the following hardware data protection
measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system
level signals during V
CC
power-up and power-down
transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
(see DC Characteristics
for voltage levels), the device does not accept any
write cycles. This protects data during V
CC
power-up
and power-down. The command register and all inter-
nal program/erase circuits are disabled. Under this
condition the device resets to the read mode. Subse-
quent writes are ignored until the V
CC
level is greater
than V
LKO
. The system must ensure that the control
pins are logically correct to prevent unintentional
writes when V
CC
is above V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be at V
IL
while OE# is at V
IH
.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing
incorrect
address and data values
or writing them in the
im-
proper sequence
resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must
issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more informa-
tion. The Read Operations table provides the read pa-
rameters, and Read Operation Timings diagram
shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
相關(guān)PDF資料
PDF描述
AM29F032B-90EE 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F032B-90EI 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F032B-90FC 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F032B-90FE 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F032B-90FI 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
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