參數(shù)資料
型號(hào)： AM29DS320GB120EIN
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
中文描述： 2M X 16 FLASH 1.8V PROM, 120 ns, PDSO48
封裝： MO-142DD, TSOP-48
文件頁數(shù)： 4/54頁
文件大?。?/td> 624K
代理商： AM29DS320GB120EIN
January 27, 2003
Am29DS320G
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Special Package Handling Instructions ..........................................5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Device Bus Operations .............................................................8
Word/Byte Configuration ................................................................8
Requirements for Reading Array Data ...........................................8
Writing Commands/Command Sequences ....................................9
Accelerated ProgramOperation .....................................................9
Autoselect Functions ......................................................................9
Simultaneous Read/Write Operations
with ZeroLatency ...........................................................................9
Standby Mode ................................................................................9
Automatic Sleep Mode ...................................................................9
RESET#: Hardware Reset Pin .....................................................10
Output Disable Mode ...................................................................10
Table 2. Top Boot Sector Addresses ...................................................11
Table 3. Top Boot SecSi
TM
Sector Addresses..................................... 12
Table 4. BottomBoot Sector Addresses ...............................................13
Table 5. BottomBoot SecSi
TM
Sector Addresses................................ 14
Autoselect Mode ..........................................................................15
Table 6. Autoselect Codes, (High Voltage Method) .............................15
Sector/Sector Block Protection and Unprotection ........................16
Table 7. Top Boot Sector/Sector Block Addresses
forProtection/Unprotection ...................................................................16
Table 8. BottomBoot Sector/Sector Block Addresses
forProtection/Unprotection ...................................................................16
Write Protect (WP#) .....................................................................17
Temporary Sector Unprotect ........................................................17
Figure 1. Temporary Sector Unprotect Operation................................. 17
Figure 2. In-SystemSector Protection/
Sector Unprotection Algorithms............................................................ 18
SecSi
TM
(Secured Silicon) Sector
Flash MemoryRegion ..................................................................19
Factory Locked: SecSi Sector Programmed and Protected At the
Factory .........................................................................................19
Customer Lockable: SecSi Sector NOT Programmed or Protected At
the Factory ...................................................................................19
Figure 3. SecSi Sector Protect Verify.................................................... 20
Hardware Data Protection ............................................................20
Low VCC Write Inhibit ..................................................................20
Write Pulse “Glitch” Protection .....................................................20
Logical Inhibit ...............................................................................20
Power-Up Write Inhibit .................................................................20
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 9. CFI Query Identification String................................................ 21
Table 10. SystemInterface String......................................................... 22
Table 11. Device Geometry Definition.................................................. 22
Table 12. Primary Vendor-Specific Extended Query............................ 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . .23
Reading Array Data ......................................................................23
Reset Command ..........................................................................24
Autoselect Command Sequence ..................................................24
Enter SecSi
TM
Sector/Exit SecSi Sector
Command Sequence ...................................................................24
Byte/Word ProgramCommand Sequence ...................................24
Unlock Bypass Command Sequence ...........................................25
Figure 4. ProgramOperation................................................................ 25
Chip Erase Command Sequence .................................................25
Sector Erase Command Sequence ..............................................26
Erase Suspend/Erase Resume Commands ................................26
Figure 5. Erase Operation.................................................................... 27
Table 13. Command Definitions........................................................... 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data#Polling ......................................................................29
Figure 6. Data#Polling Algorithm......................................................... 29
RY/BY#: Ready/Busy#.................................................................30
DQ6: Toggle Bit I ..........................................................................30
Figure 7. Toggle Bit Algorithm.............................................................. 30
DQ2: Toggle Bit II .........................................................................31
Reading Toggle Bits DQ6/DQ2 ....................................................31
DQ5: Exceeded Timng Limts ......................................................31
DQ3: Sector Erase Timer .............................................................31
Table 14. Write Operation Status .........................................................32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 8. MaximumNegative OvershootWaveform............................. 33
Figure 9. MaximumPositive OvershootWaveform.............................. 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents).................................................................... 35
Figure 11. Typical I
vs. Frequency................................................... 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.......................................................................... 36
Figure 13. Input Waveforms and Measurement Levels........................ 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14. Read Operation Timngs...................................................... 37
Figure 15. Reset Timngs...................................................................... 38
Word/Byte Configuration (BYTE#) ...............................................39
Figure 16. BYTE# Timngs for Read Operations.................................. 39
Figure 17. BYTE# Timngs for Write Operations.................................. 39
Erase and ProgramOperations ...................................................40
Figure 18. ProgramOperation Timngs................................................ 41
Figure 19. Accelerated ProgramTimng Diagram................................ 41
Figure 20. Chip/Sector Erase Operation Timngs................................. 42
Figure 21. Back-to-back Read/Write Cycle Timngs............................. 43
Figure 22. Data#Polling Timngs (During EmbeddedAlgorithms)....... 43
Figure 23. Toggle Bit Timngs (During EmbeddedAlgorithms)............ 44
Figure 24. DQ2 vs. DQ6....................................................................... 44
Temporary Sector Unprotect ........................................................45
Figure 25. Temporary Sector Unprotect Timng Diagram..................... 45
Figure 26. Sector/Sector Block Protect and Unprotect TimngDiagram46
Alternate CE#Controlled Erase and ProgramOperations ...........47
Figure 27. Alternate CE#Controlled Write (Erase/Program)
OperationTimngs................................................................................ 48
Erase And Programming Performance . . . . . . . 49
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 49
TSOP And SO Pin Capacitance. . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50
FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm.........................50
TS 048—Thin Small Outline Package ..........................................51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision A (May 14, 2002) ...........................................................52
Revision A+1 (January 3, 2003) ...................................................52
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