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參數(shù)資料
| 型號： | AM29DL400BB-120EE |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 256K X 16 FLASH 3V PROM, 120 ns, PDSO48 |
| 封裝： | MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29DL400BB-120EE |
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10
Am29DL400B
P R E L I M I N A R Y
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
相關PDF資料 |
PDF描述 |
|---|---|
| AM29DL400BB-120EI | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL400BB-120FC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL400BB-120FCB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL400BB-120FE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL400BB-120FEB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
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|---|---|
| AM29DL400BB70EC | 制造商:AMD 功能描述:* 制造商:Advanced Micro Devices 功能描述: |
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| AM29DL640G70EI | 制造商:Advanced Micro Devices 功能描述: |
| AM29DL800BB-120WBD | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 8Mbit 1M/512K x 8bit/16bit 120ns 48-Pin FBGA |
| AM29DL800BB-70SI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 8MBIT 1MX8/512KX16 70NS 44SOIC - Trays |
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