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參數(shù)資料
| 型號： | AM29DL324GB90WMI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 6 X 12 MM, 0.80 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 4/58頁 |
| 文件大小： | 875K |
| 代理商： | AM29DL324GB90WMI |
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Am29DL32xG
25686B10 December4,2006
D A T A S H E E T
GENERAL DESCRIPTION
The Am29DL32xG family consists of 32 megabit, 3.0
volt-only flash memory devices, organized as
2,097,152 words of 16 bits each or 4,194,304 bytes of
8 bits each. Word mode data appears on DQ15–DQ0;
byte mode data appears on DQ7–DQ0. The device is
designed to be programmed in-system with the stan-
dard 3.0 volt V
CC
supply, and can also be programmed
in standard EPROM programmers.
The devices are available with an access time of 70,
90, or 120 ns. The devices are offered in 48-pin TSOP,
48-ball or 63-ball FBGA, and 64-ball Fortified BGA
packages. Standard control pins—chip enable (CE#),
write enable (WE#), and output enable (OE#)—control
normal read and write operations, and avoid bus con-
tention issues.
The devices requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL32xG device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
Am29DL32xG Features
The
Secured Silicon
Sector
is an extra sector capable
of being permanently locked by AMD or customers.
The
Secured Silicon Indicator Bit
(DQ7) is perma-
nently set to a 1 if the part is
factory
locked
, and set
to a 0 if
customer lockable
. This way, customer lock-
able parts can never be used to replace a factory
locked part.
Current version of device has 256
bytes, which differs from previous versions of this
device.
Factory locked parts provide several options. The Se-
cured Silicon Sector
may store a secure, random 16
byte ESN (Electronic Serial Number), customer code
(programmed through AMD’s ExpressFlash service),
or both.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard
. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode
.
The system can also place the device into the
standby mode
. Power consumption is greatly re-
duced in both modes.
Device
DL322
DL323
DL324
Bank 1
4
8
16
Bank 2
28
24
16
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