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    參數(shù)資料
    

    


    


    
型號(hào)：
AM29DL322GT30WDI

    

    
廠商：
Spansion Inc.

    

    
英文描述：
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    
中文描述：
32兆位（4個(gè)M × 8位/ 2米x 16位），3.0伏的CMOS只，同時(shí)作業(yè)快閃記憶體

    

    
文件頁(yè)數(shù)：
13/58頁(yè)

    

    
文件大?。?/td>
875K

    

    
代理商：
AM29DL322GT30WDI


    

    

    

	
    
    
    

    
    
	
    December4,2006 25686B10
    Am29DL32xG
    11
    D A T A  S H E E T
    data on the device data outputs. Each bank remains
    enabled for read access until the command register
    contents are altered.
    See “Requirements for Reading Array Data” for more
    information. Refer to the AC Read-Only Operations
    table for timing specifications and to Figure 13 for the
    timing diagram. I
    CC1
     in the DC Characteristics table
    represents the active current specification for reading
    array data.
    Writing Commands/Command Sequences
    To write a command or command sequence (which in-
    cludes programming data to the device and erasing
    sectors of memory), the system must drive WE# and
    CE# to V
    IL
    , and OE# to V
    IH
    .
    For program operations, the BYTE# pin determines
    whether the device accepts program data in bytes or
    words. Refer to “Word/Byte Configuration” for more in-
    formation. 
    The device features an 
    Unlock Bypass
     mode to facili-
    tate faster programming. Once a bank enters the Un-
    lock Bypass mode, only two write cycles are required
    to program a word or byte, instead of four. The
    “Word/Byte Configuration” section has details on pro-
    gramming data to the device using both standard and
    Unlock Bypass command sequences.
    An erase operation can erase one sector, multiple sec-
    tors, or the entire device. Tables 3–6 indicate the ad-
    dress space that each sector occupies. The device
    address space is divided into two banks: Bank 1 con-
    tains the boot/parameter sectors, and Bank 2 contains
    the larger, code sectors of uniform size. A “bank ad-
    dress” is the address bits required to uniquely select a
    bank. Similarly, a “sector address” is the address bits
    required to uniquely select a sector.
    I
    CC2
     in the DC Characteristics table represents the ac-
    tive current specification for the write mode. The AC
    Characteristics section contains timing specification
    tables and timing diagrams for write operations.
    Accelerated Program Operation
    The device offers accelerated program operations
    through the ACC function. This is one of two functions
    provided by the WP#/ACC pin. This function is prima-
    rily intended to allow faster manufacturing throughput
    at the factory. 
    If the system asserts V
    HH
     on this pin, the device auto-
    matically enters the aforementioned Unlock Bypass
    mode, temporarily unprotects any protected sectors,
    and uses the higher voltage on the pin to reduce the
    time required for program operations. The system
    would use a two-cycle program command sequence
    as required by the Unlock Bypass mode. Removing
    V
    HH
     from the WP#/ACC pin returns the device to nor-
    mal operation. Note that the WP#/ACC pin must not be
    at V
    HH
     for operations other than accelerated program-
    ming, or device damage may result. In addition, the
    WP#/ACC pin must not be left floating or unconnected;
    inconsistent behavior of the device may result.
    Autoselect Functions
    If the system writes the autoselect command se-
    quence, the device enters the autoselect mode. The
    system can then read autoselect codes from the inter-
    nal register (which is separate from the memory array)
    on DQ7–DQ0. Standard read cycle timings apply in
    this mode. Refer to the Autoselect Mode and Autose-
    lect Command Sequence sections for more informa-
    tion.
    Simultaneous Read/Write Operations 
    with Zero Latency
    This device is capable of reading data from one bank
    of memory while programming or erasing in the other
    bank of memory. An erase operation may also be sus-
    pended to read from or program to another location
    within the same bank (except the sector being
    erased). Figure 20 shows how read and write cycles
    may be initiated for simultaneous operation with zero
    latency. I
    CC6
     and I
    CC7
     in the DC Characteristics table
    represent the current specifications for read-while-pro-
    gram and read-while-erase, respectively.
    Standby Mode
    When the system is not reading or writing to the de-
    vice, it can place the device in the standby mode. In
    this mode, current consumption is greatly reduced,
    and the outputs are placed in the high impedance
    state, independent of the OE# input. 
    The device enters the CMOS standby mode when the
    CE# and RESET# pins are both held at V
    CC
     ± 0.3 V.
    (Note that this is a more restricted voltage range than
    V
    IH
    .) If CE# and RESET# are held at V
    IH
    , but not within
    V
    CC
     ± 0.3 V, the device will be in the standby mode,
    but the standby current will be greater. The device re-
    quires standard access time (t
    CE
    ) for read access
    when the device is in either of these standby modes,
    before it is ready to read data.
    If the device is deselected during erasure or program-
    ming, the device draws active current until the
    operation is completed.
    I
    CC3
     in the DC Characteristics table represents the
    standby current specification. 
    Automatic Sleep Mode
    The automatic sleep mode minimizes Flash device en-
    ergy consumption. The device automatically enables
    this mode when addresses remain stable for t
    ACC
     +
    30 ns. The automatic sleep mode is independent of
    the CE#, WE#, and OE# control signals. Standard ad-
    dress access timings provide new data when ad-
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
AM29DL322GT30WDIN
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    
AM29DL322GT30WMF
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    
AM29DL322GT30WMFN
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    
AM29DL322GT30WMI
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    
AM29DL322GT30WMIN
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
AM29DL322GT-90EI
 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP

    

    
AM29DL323CB-90EI
 制造商:Advanced Micro Devices 功能描述:

    

    
AM29DL323DB-90EI
 制造商:Advanced Micro Devices 功能描述:

    

    
AM29DL323DT-120WDI
 制造商:Advanced Micro Devices 功能描述:

    

    
AM29DL323DT120WDIT
 制造商:Advanced Micro Devices 功能描述:

    

    
    
    
    
	
    	
    
    
     
     
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