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58
Am29BDS640G
October 31, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a
bank in the process of performing an erase or program.
Figure 31.
Latency with Boundary Crossing
into Program/Erase Bank
CLK
Address (hex)
C60
C61
C62
C63
C63
C63
C64
D60
D61
D62
D63
Read Status
(stays high)
AVD#
RDY
Data
OE#,
CE#
(stays low)
Address boundary occurs every 64 words, beginning at address
00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing
3C
3D
3E
3F
3F
3F
40
latency
RDY
latency
t
RACC
(Note 1)
(Note 2)
t
RACC
t
RACC
t
RACC
Invalid
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