參數(shù)資料
型號： AM29BDS640GTD3WSI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80
封裝： 11 X 12 MM, 0.80 MM PITCH, FBGA-80
文件頁數(shù)： 4/65頁
文件大?。?/td> 899K
代理商： AM29BDS640GTD3WSI
October 31, 2002
Am29BDS640G
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Special Handling Instructions for FBGA Package ....................8
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Device Bus Operations ....................................................11
Enhanced VersatileIO (V
IO
) Control ....................................11
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................11
Requirements for Synchronous (Burst) Read Operation ........12
8-, 16-, and 32-Word Linear Burst with Wrap Around ............12
Table 2. Burst Address Groups .......................................................12
Burst Mode Configuration Register ........................................12
Reduced Wait-State Handshaking Option ..............................13
Simultaneous Read/Write Operations with Zero Latency .......13
Writing Commands/Command Sequences ............................13
Accelerated ProgramOperation .............................................13
Autoselect Functions ..............................................................13
Standby Mode ........................................................................14
Automatic Sleep Mode ...........................................................14
RESET# Hardware Reset Input .............................................14
Output Disable Mode ..............................................................14
Hardware Data Protection ......................................................14
Write Protect (WP#) ................................................................14
Low V
CC
Write Inhibit ..............................................................15
Write Pulse “Glitch” Protection ...............................................15
Logical Inhibit ..........................................................................15
Power-Up Write Inhibit ............................................................15
V
CC
and V
IO
Power-up And Power-down Sequencing ...........15
Common Flash Memory Interface (CFI) . . . . . . .15
Table 3. CFI Query Identification String ..........................................15
Table 4. SystemInterface String .....................................................16
Table 5. Device Geometry Definition ..............................................16
Table 6. Primary Vendor-Specific Extended Query ........................17
Table 7. Sector Address Table ........................................................18
Command Definitions . . . . . . . . . . . . . . . . . . . . . .22
Reading Array Data ................................................................22
Set Burst Mode Configuration Register Command Sequence 22
Figure 1. Synchronous/Asynchronous State Diagram.................... 22
Read Mode Setting .................................................................22
Programmable Wait State Configuration ................................22
Table 8. Programmable Wait State Settings ...................................23
Reduced Wait-State Handshaking Option ..............................23
Table 9. Initial Access Cycles vs. Frequency ..................................23
Standard Handshaking Operation ..........................................23
Table 10. Wait States for Standard Handshaking ...........................23
Burst Read Mode Configuration .............................................23
Table 11. Burst Read Mode Settings ..............................................24
Burst Active Clock Edge Configuration ...................................24
RDY Configuration ..................................................................24
Configuration Register ............................................................24
Table 12. Burst Mode Configuration Register .................................24
Sector Lock/Unlock Command Sequence ..............................24
Reset Command .....................................................................24
Autoselect Command Sequence ............................................25
Table 13. Device IDs ......................................................................25
ProgramCommand Sequence ...............................................25
Unlock Bypass Command Sequence .....................................26
Figure 2. Erase Operation.............................................................. 26
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................27
Erase Suspend/Erase Resume Commands ...........................27
Figure 3. ProgramOperation......................................................... 28
Command Definitions .............................................................29
Table 14. Command Definitions ....................................................29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data#Polling .................................................................30
Figure 4. Data#Polling Algorithm.................................................. 30
RDY: Ready ............................................................................31
DQ6: Toggle Bit I ....................................................................31
Figure 5. Toggle Bit Algorithm....................................................... 31
DQ2: Toggle Bit II ...................................................................31
Table 15. DQ6 and DQ2 Indications ..............................................32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timng Limts ................................................32
DQ3: Sector Erase Timer .......................................................33
Table 16. Write Operation Status ...................................................33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 6. MaximumNegative OvershootWaveform...................... 34
Figure 7. MaximumPositive OvershootWaveform........................ 34
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Test Setup....................................................................... 36
Table 17. Test Specifications .........................................................36
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Input Waveforms and Measurement Levels................... 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
VCC and VIO Power-up ..........................................................37
Figure 10. V
CC
and V
IO
Power-up Diagram................................... 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Synchronous/Burst Read ........................................................38
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK).......................................................................... 39
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)..................................................................... 40
Figure 13. Synchronous Burst Mode Read.................................... 41
Figure 14. 8-word Linear Burst with Wrap Around......................... 41
Figure 15. Burst with RDY Set One Cycle Before Data................. 42
Figure 16. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address.......................................................... 43
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address............................................................ 44
Asynchronous Read ...............................................................45
Figure 18. Asynchronous Mode Read with Latched Addresses.... 45
Figure 19. Asynchronous Mode Read............................................ 46
Figure 20. Reset Timngs............................................................... 47
Erase/ProgramOperations .....................................................48
Figure 21. Asynchronous ProgramOperation Timngs.................. 49
Figure 22. Alternate Asynchronous ProgramOperation Timngs... 50
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