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參數(shù)資料
| 型號： | AM28F512A-90PI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Hex Inverters 14-SOIC -40 to 85 |
| 中文描述： | 64K X 8 FLASH 12V PROM, 90 ns, PDIP32 |
| 封裝： | PLASTIC, DIP-32 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 463K |
| 代理商： | AM28F512A-90PI |
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16
Am28F512A
Toggle Bit—DQ6
The device also features a “Toggle Bit” as a method to
indicate to the host system that the Embedded algo-
rithms are either in progress or completed.
Successive attempts to read data from the device at a
valid address, while the Embedded Program algorithm
is in progress, or at any address while the Embedded
Erase algorithm is in progress, will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase algorithm is completed, DQ6 will stop
toggling to indicate the completion of either Embedded
operation. Only on the next read cycle will valid data be
obtained. The toggle bit is valid after the rising edge of
the first WE# pulse of the two write pulse sequence, un-
like Data# Polling which is valid after the rising edge of
the second WE# pulse. This feature allows the user to
determine if the device is partially through the two write
pulse sequence.
tions and diagrams.
START
Fail
No
DQ6 = Toggle
?
DQ5 = 1
?
Pass
Yes
No
Read Byte
(DQ0–DQ7)
Addr = VA
Read Byte
(DQ0–DQ7)
Addr = VA
Yes
No
Yes
DQ6 = Toggle
?
VA = Byte address for programming
= XXXXh during chip erase
18880C-10
Note:
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 5.
Toggle Bit Algorithm
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