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參數(shù)資料
| 型號： | AM28F512A-120JE |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Divide-By-Twelve Decade Counter 14-SOIC 0 to 70 |
| 中文描述： | 64K X 8 FLASH 12V PROM, 120 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 5/34頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AM28F512A-120JE |
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Am28F512A
13
Embedded Programming Algorithm
The Embedded Program Setup is a command only op-
eration that stages the device for automatic program-
ming. Embedded Program Setup is performed by
writing 10h or 50h to the command register.
Once the Embedded Setup Program operation is per-
formed, the next WE# pulse causes a transition to an
active programming operation. Addresses are latched
on the falling edge of CE# or WE# pulse, whichever
happens later. Data is latched on the rising edge of
WE# or CE#, whichever happens first. The rising edge
of WE# also begins the programming operation. The
system is not required to provide further controls or
timings. The device will automatically provide an ade-
quate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data on DQ7 is equivalent to data
written to this bit (see Write Operation Status section)
at which time the device returns to Read mode.
algorithm, a typical command string, and bus operation.
Table 5.
Embedded Programming Algorithm
Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or
switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer
to Functional Description. Device is either powered-down, erase inhibit or program inhibit.
Bus Operations
Command
Comments
Standby
Write
Embedded Program Setup Command
Data = 10h or 50h
Write
Embedded Program Command
Valid Address/Data
Read
Data
# Polling to Verify Completion
Read
Available for Read Operations
START
Apply VPPH
Write Embedded Setup Program Command
Write Embedded Program Command (A/D)
Programming Completed
Yes
Data# Poll Device
Increment Address
No
18880C-7
Figure 2.
Embedded Programming Algorithm
Last Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM28F512A-120JEB | Divide-By-Twelve Decade Counter 14-PDIP 0 to 70 |
| AM28F512A-120JI | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms |
| AM28F512A-120JIB | Divide-By-Twelve Decade Counter 14-PDIP 0 to 70 |
| AM28F512A-120PC | Divide-By-Twelve Decade Counter 14-SO 0 to 70 |
| AM28F512A-120PCB | Divide-By-Twelve Decade Counter 14-SO 0 to 70 |
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