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參數(shù)資料
| 型號： | AM28F256 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial-in shift registers with output registers and open collector outputs 16-PDIP 0 to 70 |
| 中文描述： | 256千比特（32畝× 8位）的CMOS 12.0伏，整體擦除閃存 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 493K |
| 代理商： | AM28F256 |
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14
Am28F256
Figure 2.
AC Waveforms For Erase Operations
ANALYSIS OF ERASE TIMING WAVEFORM
Note:
This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite
Programming algorithm.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.
The erase pulse occurs in section C.
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.
Note:
An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
After each erase operation each byte must be verified.
The byte address to be verified must be supplied with
Addresses
CE
#
OE
#
WE
#
Data
V
PP
V
CC
11559G-7
20h
20h
Section
A0h
Data
Out
Bus Cycle
Write
Write
Time-out
Write
Time-out
Read
Standby
Command
20h
20h
N/A
A0h
N/A
Compare
Data
N/A
Function
Erase
Setup
Erase
Erase
(10 ms)
Erase-
Verify
Transition
(6 μs)
Erase
Verification
Proceed per
Erase
Algorithm
A
B
D
E
F
C
G
A
B
D
E
F
C
G
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM28F256-120EE | Serial-out shift registers with input latches 16-SOIC 0 to 70 |
| AM28F256-120EI | Serial-out shift registers with input latches 16-SOIC 0 to 70 |
| AM28F256-120FC | Serial-out shift registers with input latches 16-SOIC 0 to 70 |
| AM28F256-120FCB | Serial-out shift registers with input latches 16-SOIC 0 to 70 |
| AM28F256-120FE | Serial-out shift registers with input latches 16-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM28F256-120C3/BUA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| AM28F256-120C3/BXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| AM28F256-120C3JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| AM28F256-120C3JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| AM28F256-120C3PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
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