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參數(shù)資料
| 型號： | AM27C64-120DI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
| 中文描述： | 8K X 8 UVPROM, 120 ns, CDIP28 |
| 封裝： | WINDOWED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 172K |
| 代理商： | AM27C64-120DI |
Am27C64
9
TEST CONDITIONS
Table 1.
Test Specifications
SWITCHING TEST WAVEFORM
KEY TO SWITCHING WAVEFORMS
2.7 k
C
L
6.2 k
5.0 V
Device
Under
Test
11419E-7
Figure 3.
Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition
-45, -55,
-70
All
others
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
≤
20
ns
Input Pulse Levels
0.0–3.0
0.45–2.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
2.4 V
0.45 V
Input
Output
Test Points
2.0 V
2.0 V
0.8 V
0.8 V
11419E-8
3 V
0 V
Input
Output
1.5 V
1.5 V
Test Points
Note:
For C
L
= 100 pF
Note:
For C
L
= 30 pF
KS000010-PAL
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
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| AM27C64-120JE | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
| AM27C64-120JI | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
| AM27C64-120PC | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
| AM27C64-120PE | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
| AM27C64-120PI | Octal D-Type Flip-Flops With Clock Enable 20-SOIC 0 to 70 |
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