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參數(shù)資料
| 型號： | AM27C512-55DI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-PDIP 0 to 70 |
| 中文描述： | 512千比特（64畝× 8位）的CMOS存儲器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 168K |
| 代理商： | AM27C512-55DI |
6
Am27C512
mon connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the out-
put pins are only active when data is desired from a
particular memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 μF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
V
CC
and V
SS
to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7 μF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for each eight devices. The loca-
tion of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
Notes:
1. V
H
= 12.0 V
±
0.5 V.
2. X = Either V
IH
or V
IL
.
3.
A1–A8 and A10–15 = V
IL
4. See DC Programming Characteristics for V
PP
voltage during programming.
Mode
CE#
OE#/V
PP
A0
A9
Outputs
Read
V
IL
V
IL
X
X
D
OUT
Output Disable
X
V
IH
X
X
High Z
Standby (TTL)
V
IH
X
X
X
High Z
Standby (CMOS)
V
CC
±
0.3 V
X
X
X
High Z
Program
V
IL
V
PP
X
X
D
IN
Program Verify
V
IL
V
IL
X
X
D
OUT
Program Inhibit
V
IH
V
PP
X
X
High Z
Autoselect
(Note 3)
Manufacturer Code
V
IL
V
IL
V
IL
V
H
01h
Device Code
V
IL
V
IL
V
IH
V
H
91h
相關PDF資料 |
PDF描述 |
|---|---|
| AM27C512-70DC | Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SO 0 to 70 |
| AM27C512-70DCB | Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SO 0 to 70 |
| AM27C512-70DE | Quad bistable latches 16-SOIC 0 to 70 |
| AM27C512-70DEB | 512 Kilobit (64 K x 8-Bit) CMOS EPROM |
| AM27C512-70DI | 512 Kilobit (64 K x 8-Bit) CMOS EPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM27C512-70DC | 制造商:Rochester Electronics LLC 功能描述: |
| AM27C51275DC | 制造商:AMD 功能描述:New |
| AM27C512-75DC | 制造商:Advanced Micro Devices 功能描述:EPROM, 64K x 8, 28 Pin, Ceramic, DIP |
| AM27C51290DC | 制造商:Advanced Micro Devices 功能描述: |
| AM27C512DC | 制造商:Advanced Micro Devices 功能描述: |
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