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參數(shù)資料
| 型號(hào)： | AM27C256-55DI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | PROM |
| 英文描述： | Quad 2-input positive-NOR buffers with open collector outputs 14-SOIC 0 to 70 |
| 中文描述： | 32K X 8 UVPROM, 55 ns, CDIP28 |
| 封裝： | WINDOWED, CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | AM27C256-55DI |
10
Am27C256
AC CHARACTERISTICS
Caution:
Do not remove the device from (or insert it into) a socket or board that has V
PP
or V
CC
applied.
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
Notes:
1. OE# may be delayed up to t
ACC
– t
OE
after the falling edge of the addresses without impact on t
ACC
.
2. t
DF
is specified from OE# or ‘CE#, whichever occurs first.
PACKAGE CAPACITANCE
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz.
Parameter Symbols
Description
Test Setup
Am27C256
Unit
JEDEC
Standard
-45
-55
-70
-90
-120 -150 -200 -255
t
AVQV
t
ACC
Address to Output Delay
CE#,
OE# = V
IL
Max
45
55
70
90
120
150
200
250
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
45
55
70
90
120
150
200
250
ns
t
GLQV
t
OE
Output Enable to Output
Delay
CE# = V
IL
Max
30
35
40
40
50
50
50
50
ns
t
EHQZ
t
GHQZ
t
DF
(Note 2)
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
Max
25
25
25
25
30
30
30
30
ns
t
AXQX
t
OH
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
Min
0
0
0
0
0
0
0
0
ns
Addresses
CE#
OE#
Output
08007I-9
Addresses Valid
High Z
High Z
t
CE
Valid Output
2.4
0.45
2.0
0.8
2.0
0.8
t
ACC
(Note 1)
t
OE
t
DF
(Note 2)
t
OH
Parameter Symbol
Parameter
Description
Test Conditions
CDV028
PL 032
PD 028
Unit
Typ
Max
Typ
Max
Typ
Max
C
IN
Input Capacitance
V
IN
= 0
8
12
8
12
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
8
12
8
10
pF
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