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| 型號(hào)： | AM24LC21IN |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21IN |
AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
AC Electrical Characteristics
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
4/13
Standard Mode
Vcc=4.5V~5.5V
Fast mode
Min
0.6
1.3
Symbol
Parameter
Min
4
4.7
Max
100
Max
400
Unit
Remarks
F
CLK
T
H
T
L
Clock frequency
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
Start condition hold
time
Start
setup time
Data input hold time
Data input setup
time
Stop
setup time
Output valid from
clock
Khz
us
us
T
R
1
0.3
us
(Note1)
T
F
0.3
0.3
us
(Note1)
T
HD(ST)
4
0.6
us
After this period the first
clock pulse is generated
Only relevant for
repeated start condition
(Note 2)
T
SU(ST)
condition
4.7
0.6
us
T
HD(DI)
0
0
us
T
SU(DI)
0.25
0.1
us
T
SU(STP)
condition
4
0.6
us
T
AA
3.5
0.9
us
(Note 2)
T
BUF
Bus free time
4.7
1.3
us
Time the bus must be
free before a new
transmission can start
T
OF
Output fall time from
V
IH(min)
to V
IL(max)
Input
filter
suppression
and SCL pins)
Write cycle time
Output valid from
V
CLK
VCLK high time
VCLK low time
Mode transition time
Transmit only power
up time
0.25
20+0.1C
B
0.25
us
(Note 1), C
B
≤
100pF
T
SP
spike
(SDA
0.05
0.05
us
(Note 3)
T
WR
10
10
ms
Byte or page mode
T
VAA
2
1
T
VH
T
VL
T
VHZ
4
4.7
0.6
1.3
0.5
0.5
T
VPU
0
0
Endurance
1M
1M
cycles mode (Note 4)
0
C, V
CC
=5V, Block
Note 1.
Not 100% tested. C
B
=total capacitance of one bus line in pF.
Note 2.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the
falling edge of SCL to avoid unitended generation of start or stop conditions
Note 3.
The combined T
SP
and V
hys
specifications are due to new schmitt trigger inputs which provide improved noise and spike
suppression. This eliminates the need for a T
l
specification for standard operation.
Note 4.
This parameter is not tested but ensured by characterization.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM24LC21IS | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21ISA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21N | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21NA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM24LC21INA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21IS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21ISA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21NA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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