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| 型號(hào)： | AM2404SA |
| 英文描述： | 2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM |
| 中文描述： | 2線串行4K的位（512 × 8）的CMOS電可擦除可編程ROM |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | AM2404SA |
2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM
AM24LC04
Functional Description (Continued)
Acknowledge
Each receiving device, when addressed, is obliged
to generate an acknowledge after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
acknowledge bit. The device that acknowledges,
has to pull down the SDA line during the
acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable
the master to generate the STOP condition. (Shown
in Figure 3)
Devices Addressing
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
Write Operations
Byte Write
Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated a acknowledge bit during the
ninth clock cycle.
Therefore the next byte transmitted by the master is
the word address and will be written into the address
pointer of the AM24LC04. After receiving another
acknowledge signal from the AM24LC04 the master
device will transmit the data word to be written into
the addressed memory location. The AM24LC04
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC04 will not
generate acknowledge signals. (Shown in Figure 4)
Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC04 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 16 data bytes to the AM24LC04 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
Anachip Corp.
www.anachip.com.tw
Rev.A2 Oct 8, 2003
5/12
ATC
device code (1010) for the AM24LC04, 3-bit device
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I
2
C EEPROMs use and
internal protocol that defines a PAGE BLOCK size of
4K bits. The eighth bit of slave address determines if
the master device wants to read or write to the
AM24LC04. (Refer to table B).
The
AM24LC04
monitor
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Table B
Operation
Control Code
the
bus
for
its
Chip
Select
A2 A1 A0
A2 A1 A0
R/W
Read
Write
1010
1010
1
0
A1, A2 are used to access device address for
AM24LC04; A0 is no connect.
transmitted a stop condition. After the receipt of
each byte, the four lower order address pointer bits
are internally incremented by one. The higher order
five bits of the word address remains constant. If the
master should transmit more than 16 bytes prior to
generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once
the stop condition is received an internal write cycle
will begin. (Shown in Figure 5).
Acknowledge Polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle , then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM2404VS | 制造商:ANACHIP 制造商全稱:Anachip Corp 功能描述:2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM |
| AM2404VSA | 制造商:ANACHIP 制造商全稱:Anachip Corp 功能描述:2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM |
| AM-2405-F180-W | 制造商:HAN TOUCH 功能描述:TOUCH SCREEN, RES, 533.4x301; Meter Display Type:Analogue Resistive; Display Size:533.4mm x 301mm; Supply Voltage Range:5V DC; Operating Temperature Min:-10C; Operating Temperature Max:60C; Supply Voltage Range DC:5V |
| AM24070001 | 功能描述:24MHz ±30ppm 晶體 12pF -40°C ~ 85°C 表面貼裝 4-SMD 制造商:txc corporation 系列:AM 包裝:* 零件狀態(tài):有效 類型:MHz 晶體 頻率:24MHz 頻率穩(wěn)定度:±50ppm 頻率容差:±30ppm 負(fù)載電容:12pF ESR（等效串聯(lián)電阻）:- 工作模式:- 工作溫度:-40°C ~ 85°C 等級(jí):- 安裝類型:表面貼裝 封裝/外殼:4-SMD 大小/尺寸:0.126" 長(zhǎng) x 0.098" 寬（3.20mm x 2.50mm） 高度:0.028"（0.70mm） 標(biāo)準(zhǔn)包裝:3,000 |
| AM2-46 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GENERAL-PURPOSE PHOTOVOLTAIC CELL |
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