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| 型號(hào)： | AM188ER-25KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CA-BAYONET |
| 中文描述： | 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 55/112頁 |
| 文件大?。?/td> | 2878K |
| 代理商： | AM188ER-25KCW |
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Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
55
DRAFT
data register address, either I/O-mapped or memory-
mapped, should be specified as a byte destination for
the DMA by writing the address of the register into the
DMA destination low and DMA destination high regis-
ters. The destination address (the address of the trans-
mit data register) should be configured as a constant
throughout the DMA operation. The asynchronous se-
rial port transmitter acts as the synchronizing device;
therefore, the DMA channel should be configured as
destination-synchronized.
DMA Operation
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (two regis-
ters), a 20-bit destination address (two registers), a 16-
bit transfer count register, and a 16-bit control register.
The DMA transfer count register (DTC) specifies the
number of DMA transfers to be performed. Up to 64K
transfers can be performed with automatic termination.
The DMA control registers define the channel opera-
tion. All registers can be modified during any DMA ac-
tivity. Any changes made to the DMA registers are
reflected immediately in DMA operation.
The Am188ER microcontroller’s maximum DMA trans-
fer rates are half that of those listed in Table 9 for the
Am186ER microcontroller.
Table 9.
Am186ER Microcontroller Maximum DMA
Transfer Rates
Asynchronous Serial Port/DMA Transfers
The enhanced Am186ER/Am188ER microcontrollers
can DMA to and from the asynchronous serial port.
This is accomplished by programming the DMA con-
troller to perform transfers between a data buffer (lo-
cated either in memory or I/O space) and an
asynchronous serial port data register (SPTD or
SPRD). Note that when a DMA channel is in use by the
asynchronous serial port, the corresponding external
DMA request signal is deactivated.
For DMA
from
the asynchronous serial port, the re-
ceive data register address, either I/O-mapped or
memory-mapped, should be specified as a byte source
for the DMA by writing the address of the register into
the DMA Source and DMA Source High registers. The
source address (the address of the receive data regis-
ter) should be configured as a constant throughout the
DMA. The asynchronous serial port receiver acts as
the synchronizing device; therefore, the DMA channel
should be configured as source- synchronized.
DMA Channel Control Registers
Each DMA control register determines the mode of op-
eration for the particular DMA channel. This register
specifies the following:
n
Mode of synchronization
n
Whether bytes or words are transferred (Am186ER
microcontroller only)
n
Whether an interrupt is generated after the last
transfer
n
Whether DMA activity ceases after a programmed
number of DMA cycles
n
Relative priority of the DMA channel with respect to
the other DMA channel
n
Whether the source address is incremented, decre-
mented, or maintained constant after each transfer
n
Whether the source address addresses memory or
I/O space
n
Whether the destination address is incremented,
decremented, or maintained constant after trans-
fers
n
Whether the destination address addresses mem-
ory or I/O space
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles, except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold takes
priority over an internal DMA cycle.
Because an interrupt request, other than an NMI, can-
not suspend a DMA operation and the CPU cannot ac-
cess memory during a DMA cycle, interrupt latency
time suffers during sequences of continuous DMA cy-
cles. An NMI request, however, causes all internal
DMA activity to halt. This allows the CPU to respond
quickly to the NMI request.
Synchronization Type
Maximum DMA
Transfer Rate (Mbyte/s)
50
MHz
MHz
12.5
10
12.5
10
40
33
MHz
8.25
8.25
25
MHz
6.25
6.25
Unsynchronized
Source Synch
Destination Synch
(CPU needs bus)
Destination Synch
(CPU does not need bus)
8.33
6.6
5.5
4.16
10.00
8
6.6
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM188ER-25KI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| AM188ER-25KIW | 制造商:Advanced Micro Devices 功能描述:MCU 16-bit E86 CISC ROMLess 3.3V 100-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:MCU 16-bit E86 CISC ROMLess 3.3V 100-Pin PQFP |
| AM188ER-25VC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| AM188ER-25VCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM |
| AM188ER-25VD\\W | 制造商:Advanced Micro Devices 功能描述: |
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