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參數(shù)資料
| 型號(hào)： | ALVD-FREQ-F-N15-L |
| 廠商： | ABRACON CORP |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 0.75 MHz - 800 MHz, LVDS OUTPUT |
| 封裝： | CERAMIC, SMD, 6 PIN |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | ALVD-FREQ-F-N15-L |
Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Voltage Control (Vc)
Frequency Pullability
Linearity
Jitter (12KHz - 20MHz)
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
|||||||||||||||
ALVD SERIES
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
STANDARD SPECIFICATIONS:
APPLICATIONS:
SONET, xDSL
SDH, CPE
STB
FEATURES:
Based on a proprietary digital multiplier
Tri-State Output
Low Phase Jitter
155.52MHz, 311.04MHz, and 622.08MHz applications
2.5V to 3.3V +/- 5% operation
Ceramic SMD, low profile package
rev2.1-8/05
PARAMETERS
PECL
750 KHz to 800 MHz
0°C to + 70°C (see options)
- 55°C to + 125°C
± 50 ppm max. (see options)
2.5V to 3.3 Vdc ± 5%
0.3VDC min, 1.65VDC typ, 3.0VDC max
± 100 ppm
5% typ, 10% max.
RMS phase jitter 3pS typ. < 5pS max. period jitter < 35pS peak to peak
Phase Noise
Tri-State Function
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100kHz Offset from 622.08MHz
“1” (VIH > 0.7*VDD) or open: Oscillation/ “0” (VIH > 0.3*VDD) No Oscillation/Hi Z
5.08 x 7.0 x 1.8mm
Supply Current (IDD)
Symmetry (Duty Cycle)
Output Logic High
Output Logic Low
Clock Rise time (tr) @ 20/80%
Clock Fall time (tf) @ 80/20%
65mA (Fo < 96MHz), 100mA (Fo < 700.00MHz)
45% min, 50% typical, 55% max.
VDD -1.025V min, VDD -0.880V max.
VDD -1.810V min, VDD -1.620V max.
0.6nSec typical, 1.5ns max
LVDS
Supply Current (IDD) [Fout = 212.50MHz]
Output Clock Duty Cycle @ 1.25V
Output Differential Voltage (VOD)
VDD Magnitude Change (
VOD)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
]
Offset Magnitude Voltage[RL = 100
]
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (tr) [RL=100
, CL=10pF]
Differential Clock Fall Time (tf) [RL=100
, CL=10pF]
CMOS
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]
Output Clock Duty Cycle [Measured @ 50% VDD]
1.2ns typical, 1.6ns max
45% min, 50% typical, 55% max
45mA max (Fo < 96MHz), 80mA max (Fo < 700MHz)
45% min, 50% typical, 55% max
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
VOH = 1.4V typical, 1.6V max
VOL = 0.9V min, 1.1V typical
VOS = 1.125V min, 1.2V typical, 1.375V max
VOS = 0mV min, 3mV typical, 25mV max
±1
A typical, ±10A max
0.2ns min, 0.7ns typical, 1.0ns max
: PRELIMINARY
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