參數(shù)資料
型號(hào): ALD500R-50QE
廠商: Advanced Linear Devices, Inc.
英文描述: PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE
中文描述: 精密集成了模擬處理器,高精度電壓基準(zhǔn)
文件頁數(shù): 5/12頁
文件大?。?/td> 93K
代理商: ALD500R-50QE
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
5
DC & AC ELECTRICAL CHARACTERISTICS
T
A
= 25
°
C V supply =
±
5.0V unless otherwise specified; C
AZ
= C
REF
= 0.47
μ
f
500RAU
Typ
500RA
Typ
500R
Typ
0.6
Parameter
Supply Current
Symbol
I
S
Min
Max
1.0
Min
Max
1.0
Min
Max
1.0
Unit
mA
Test Conditions
V
+
= 5V ,
A =1,B=1
0.6
0.6
Power Dissipation
P
D
10
10
10
mW
V supply=
±
5V
Positive Supply Range
V
+S
4.5
5.5
4.5
5.5
4.5
5.5
V
Note 4
Negative Supply
Range
V
-S
-4.5
-5.5
-4.5
-5.5
-4.5
-5.5
V
Note 4
Comparator Logic 1,
Output High
V
OH
4
4
4
V
I
SOURCE
= 400
μ
A
Comparator Logic 0,
Output Low
V
OL
0.4
0.4
0.4
V
I
SINK
= 1.1mA
Logic 1, Input High
Voltage
V
IH
3.5
3.5
3.5
V
Logic 0, Input Low
Voltage
V
IL
1
1
1
V
Logic Input Current
I
L
0.01
0.01
0.01
μ
A
Comparator Delay
t
D
1
1
1
μ
sec
Note 5
Figure 3. ALD500R TIMING DIAGRAM
~
~
~
66.667 msec.
123,093
Clock Pulses
Positive Input Signal
Negative Input Signal
~
66.667 msec.
0.5416
μ
s
123,093
Clock Pulses
~
~
C
OUT
B INPUT
A INPUT
1.8432 MHz Clock
1 Conversion Cycle
Auto Zero
Phase
Input Signal
Integration
Phase
Reference
Voltage
Deintegration
Phase
Integrator Zero
Phase
Auto Zero
Phase
Fixed number
of clock pulses
by design.
Variable
number of
clock pulses.
~
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed period of
approx.1 msec.
At V
MAX,
max. number of
clock pulses
NOT VALID
Stop counter upon
detection of comparator
output going from high
to low state.
START DEINTEGRATION CYCLE
START INTEGRATION CYCLE
START
CONVERSION
CYCLE
~
~
~
START INTEGRATOR ZERO CYCLE
C
NOT VALID
REPEAT
CONVERSION
CYCLE
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ALD500R-50PE PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE
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