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參數(shù)資料
| 型號： | ALD500ASCL |
| 廠商： | Advanced Linear Devices Inc |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 17BIT DUAL 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 位數(shù)： | 17 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | * |
| 其它名稱： | 1014-1184 |
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
3
(integrate cycle)
(1)
VX = VINT - (VREF . tDINT / RINT . CINT)
(deintegrate cycle)
(2)
Combining equations 1 and 2 results in:
VIN / VREF = -tDINT / tINT
(3)
where:
Vx
= An offset voltage used as starting voltage
VINT = Voltage change across CINT during tINT and
during tDINT (equal in magnitude)
VIN
= Average, or an integrated, value of input voltage
to be measured during tINT (Constant VIN)
tINT = Fixed time period over which unknown voltage is
integrated
tDINT = Unknown time period over which a known
reference voltage is integrated
VREF = Reference Voltage
CINT = Integrating Capacitor value
RINT = Integrating Resistor value
Actual data conversion is accomplished in two phases: Input
Signal Integration Phase and Reference Voltage Deintegration
Phase.
The integrator output is initialized to 0V prior to the start of
Input Signal Integration Phase. During Input Signal Integration
Phase, internal analog switches connect VIN to the buffer
input where it is maintained for a fixed integration time period
(tINT). This fixed integration period is generally determined by
a digital counter
controlled by a crystal oscillator. The
application of VIN causes the integrator output to depart 0V at
a rate determined by VIN and a direction determined by the
polarity of VIN.
The Reference Voltage Deintegration Phase is initiated
immediately after tINT, within 1 clock cycle. During Reference
Voltage Deintegration Phase, internal analog switches connect
a reference voltage having a polarity opposite that of VIN to
the integrator input. Simultaneously the same digital counter
controlled by the same crystal oscillator used above is used to
start counting clock pulses.
The Reference Voltage
Deintegration Phase is maintained until the comparator output
inside the dual slope analog processor changes state, indicating
the integrator has returned to 0V. At that point the digital
counter is stopped. The Deintegration time period (tDINT), as
measured by the digital counter, is directly proportional to the
magnitude of the applied input voltage.
After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
reset to zero through an Integrator Zero Phase and an Auto
Zero Phase so that the next conversion can begin again. In
practice, this process is usually automated so that analog-to-
digital conversion is continuously updated. The digital control
is handled by a microprocessor or a dedicated logic controller.
The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.
Figure 2. Basic Dual-Slope Converter
S1
CINT
VINT
RINT
SWITCH DRIVER
CONTROL
LOGIC
POLARITY CONTROL
REF
SWITCHES
INTEGRATOR
COMPARATOR
PHASE
CONTROL
ANALOG
INPUT
(VIN)
OUTPUT
INTEGRATOR
VIN
≈ VFULL SCALE
VIN
≈ 1/2 VFULL SCALE
tINT
tDINT
VINT = 4.1V MAX
AB
Figure 2. Basic Dual-Slope Converter
+
-
VOLTAGE
REFERENCE
COUT
POLARITY
DETECTION
-
tDINT
VX
≈ 0
MICROCONTROLLER
(CONTROL LOGIC
+ COUNTER)
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