Supply voltage, V+
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ALD4702ASBL
寤犲晢锛� Advanced Linear Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 2/9闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC OPAMP GP R-R CMOS QUAD 14SOIC
妯欐簴鍖呰锛� 56
鏀惧ぇ鍣ㄩ鍨嬶細 閫氱敤
闆昏矾鏁�(sh霉)锛� 4
杓稿嚭椤炲瀷锛� 鎺ㄦ尳寮忥紝婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 2.8 V/µs
澧炵泭甯跺绌嶏細 1.7MHz
闆绘祦 - 杓稿叆鍋忓锛� 1pA
闆诲 - 杓稿叆鍋忕Щ锛� 1000µV
闆绘祦 - 闆绘簮锛� 4mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 8mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4 V ~ 12 V锛�±2 V ~ 6 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 14-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 14-SOIC
鍖呰锛� 绠′欢
ALD4702A/ALD4702B
Advanced Linear Devices
2 of 9
ALD4702
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+ referenced to V-
-0.3V to V++10.6V
Supply voltage, VS referenced to V-
卤5.3V
Differential input voltage range
-0.3V to V+ +0.3V
Power dissipation
600 mW
Operating tempurature range SBL, PBL packages
0掳C to +70掳C
DB package
-55掳C to +125掳C
Storage tempurature range
-65掳C to +150掳C
Lead tempurature, 10 seconds
+260掳C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
Supply
VS
卤2.0
卤5.0
卤2.0
卤5.0 卤2.0
卤5.0
V
Dual Supply
Voltage
V+
4.0
10.0
4.0
10.0
4.0
10.0
V
Single Supply
Input Offset
VOS
1.0
2.0
5.0
mV
RS 鈮� 100K
Voltage
2.0
3.5
6.5
mV
0掳C 鈮� TA 鈮� +70掳C
Input Offset
IOS
1.0
25
1.0
25
1.0
25
pA
TA = 25掳C
Current
240
pA
0掳C 鈮� TA 鈮� +70掳C
Input Bias
IB
1.0
30
1.0
30
1.0
30
pA
TA = 25掳C
Current
300
pA
0掳C 鈮� TA 鈮� +70掳C
Input Voltage
VIR
-0.3
5.3
-0.3
5.3
-0.3
5.3
V
V+ = +5V
Range
-2.8
+2.8
-2.8
+2.8
-2.8
+2.8
V
VS = 卤2.5V
Input
RIN
1012
Resistance
Input Offset
TCVOS
77
7
V/掳CRS 鈮� 100K
Voltage Drift
Power Supply
PSRR
65
83
65
83
60
83
dB
RS 鈮� 100K
Rejection Ratio
65
83
65
83
60
83
0掳C 鈮� TA 鈮� +70掳C
Common Mode
CMRR
65
83
65
83
60
83
dB
RS 鈮� 100K
Rejection Ratio
65
83
65
83
60
83
0掳C 鈮� TA 鈮� +70掳C
Large Signal
AV
15
28
15
28
12
28
V/mV
RL = 10K
Voltage Gain
100
V/mV
RL 鈮� 1M
Output
VO low
0.002
0.01
0.002 0.01
0.002
0.01
RL = 1M Single supply
Voltage
VO high
4.99
4.998
4.99
4.998
4.99
4.998
V
0掳C 鈮� TA 鈮� +70掳C
Range
VO low
-2.44
-2.40
-2.44 -2.40
-2.44
-2.40
V
RL = 10K Dual supply
VO high
2.40
2.44
2.40
2.44
2.40
2.44
V
0掳C 鈮� TA 鈮� +70掳C
Output Short
ISC
88
8
mA
Circuit Current
Supply
IS
4.0
6.0
4.0
6.0
4.0
6.0
mA
VIN = 0V No Load
Current
Power
PD
20
30
20
30
20
30
mW
Both amplifiers
Dissipation
VS = 卤2.5V
Input
CIN
11
1
pF
Capacitance
Bandwidth
BW
0.7
1.5
0.7
1.5
0.7
1.5
MHz
Slew Rate
SR
1.1
1.9
1.1
1.9
1.1
1.9
V/sAV = +1 RL = 10K
Rise time
tr
0.2
sRL = 10K
Overshoot
10
%
RL = 10K CL = 100pF
Factor
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25掳C VS = 卤2.5V unless otherwise specified
4702A
4702B
4702
Test
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Conditions
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
ALD4702B 鍒堕€犲晢:ALD 鍒堕€犲晢鍏ㄧū:Advanced Linear Devices 鍔熻兘鎻忚堪:QUAD 5V RAIL-TO-RAIL PRECISION OPERATIONAL AMPLIFIER
ALD4702BDB 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Operational Amplifier
ALD4702BPB 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 5V Precision RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel
ALD4702BPBL 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 2.0mV Quad Prec CMOS RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel
ALD4702BSB 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 5V Precision RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel
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