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參數(shù)資料
| 型號： | ALD1000 |
| 英文描述： | ALD1000 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | ALD1000 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計(jì)。 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 209K |
| 代理商： | ALD1000 |
4
ALD1000
PIN ASSIGNMENTS
PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
XTR GND
Disable
Select
C
C2
C
C1
P
1
N
1
A
COM
+V
S
V
OUT1
V
INP1
R
GB1
R
GA1
V
INN1
V
INN2
R
GA2
R
GB2
V
INP2
V
OUT2
–V
S
N
2
P
2
E
X
P
X
N
C
Bias
V
ERR
Power ground pin.
A 5V signal puts the internal drive in a high impedance state and limits the external drive capacity.
Selects the SWOP amp input. A 5V signal selects inputs N1 and P1.
C
C1
and C
C2
are for the external compensation capacitor.
C
C1
and C
C2
are for the external compensation capacitor.
Non-inverting input to the XTR SWOP amp 1.
Inverting input to the XTR SWOP amp 1.
Signal ground for the instrumentation amplifiers.
Positive power supply voltage.
Output of the instrumentation amplifier 1.
Non-inverting input to instrumentation amplifier 1.
Gain set resistor for instrumentation amplifier 1.
Gain set resistor for instrumentation amplifier 1.
Inverting input of instrumentation amplifier 1.
Inverting input of instrumentation amplifier 2.
Gain set resistor for instrumentation amplifier 2.
Gain set resistor for instrumentation amplifier 2.
Non-inverting input to instrumentation amplifier 2.
Output of the instrumentation amplifier 2.
Negative power supply voltage.
Inverting input to the XTR SWOP amp 2.
Non-inverting input to the XTR SWOP amp 2.
Inverting input (emitter) of the output transconductance amplifier.
Base drive for an external, PNP, driver transistor (optional).
Base drive for an external, NPN, driver transistor (optional).
Output (collector) of the output transconductance amplifier.
Open collector output indicating an internal overcurrent condition.
Open collector output indicating an overvoltage condition.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN CONFIGURATION
Top View
28-Lead
SOIC
XTR GND
Disable
Select
C
C2
C
C1
P
1
N
1
A
COM
+V
S
V
OUT1
V
INP1
R
GB1
R
GA1
V
INN1
V
ERR
Bias
C
X
N
X
P
E
P
2
N
2
–V
S
V
OUT2
V
INP2
R
GB2
R
GA2
V
INN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IA
IA
TA
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