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參數(shù)資料
| 型號(hào)： | AL5DA036 |
| 廠商： | AverLogic Technologies, Inc. |
| 英文描述： | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| 中文描述： | 3.3V，5V的異步雙端口SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 88K |
| 代理商： | AL5DA036 |
2003 -Copyright by AverLogic Technologies, Corp. 1-F-PMK008-0001
AL5DAxxxx
3.3V, 5V Asynchronous Dual-Port SRAM
1k/2k/4K/8K/16K/32K x 8/9/16/18-bit
Features
!
True dual port memory cells up to 256/288Kb
!
Fully asynchronous dual-port SRAM aimed at communications market
!
Max. access time: 30 ns
!
Separate upper byte and lower byte control for multiplexed bus compatibility (only for 16/18 bit
devices)
!
Supports byte write/read for 16/18 bit devices
!
On-chip arbitration logic support 3 modes: Busy, Interrupt and Semaphore
-
Busy scheme circuit arbitrate between 2 ports
-
interrupt mechanism allow port to port communication
-
Full hardware support of semaphore to permit software handshaking between ports
!
Versatile pin select for Master or Slave mode:
IH
V
S
M/
=
for
BUSY
output flag on master;
V
S
M/
=
!
Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one
device
!
Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)
!
3.3v and 5v series low power respectively
!
Compatible and functionally equivalent to IDT or Cypress
!
Available in 52-PLCC, 68-PLCC, 84-PLCC, 64-TQFP/STQFP, 80-TQFP, 100-TQFP
Architecture
IL
for
BUSY
input flag on slave
S
M/
L
CE
L
OE
UB
L
L
LB
R
CE
OE
UB
LB
R
R
R
7/8L
-
0L
IO
-15/17L
8/9L
IO
R
W
R/
BUSY
SEM
INT
)
,
(
2
1
R
R
)
(
2
R
L
W
R/
BUSY
SEM
INT
)
,
(
2
1
L
L
(
2
)
L
15/17R
-
8/9L
IO
7/8R
-
0R
IO
9R
-
0R
A
-14R
10R
A
9L
-
0L
A
14L
-
10L
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AL5DA125 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA132 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA134 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA138 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA139 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AL5DA125 | 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA132 | 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA134 | 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA138 | 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA139 | 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
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