參數(shù)資料
型號(hào)： AL4CS241
英文描述： (512 x9. 1k x9. 2k x9. 4k x9. 8k x9) Synchronous FIFO
中文描述： （512 X9熱賣。經(jīng)銷商X9熱賣。2k X9熱賣。4K的X9熱賣。8K的X9熱賣）同步FIFO
文件頁(yè)數(shù)： 12/25頁(yè)
文件大?。?/td> 2044K
代理商： AL4CS241
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
December 14, 2001
12
9.0 Multiple Devices Bus Expansion and Cascading
9.1 Width Expansion Configuration
Simply connecting the corresponding input controls signals of multiple devices may increase data bus
width. A composite flag should be created for each of the end-point status flags (/EF and /FF). The
partial status flags (/PAE and /PAF) can be detected from any one device. Figure 15 demonstrates an
18-bit word width data bus by using two AL4CS211/221/231/241/251s. Any word width expansion
can be attained by adding additional AL4CS211/221/231/241/251s. When these devices are in a
Width Expansion Configuration, the Read Enable 2 (/REN2) control input can be grounded (see
Figure 15). In this configuration, theWriteEnable2<Load> (WEN2</LD>) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
18-Bit Data In Bus
AL4CS2x1
/WEN1
WCLK
Q[8:0]
WEN2
/PAE
RCLK
/REN1
/OE
/
/
/PAF
/
D
/
AL4CS2x1
/WEN1
WCLK
Q[8:0]
WEN2
/PAE
RCLK
/REN1
/OE
/
/
/PAF
/
D
/
Write Clock
Write Enable
Write Enable2
Programmable
Write Controls
Write Controls
G
Read Controls
Read Clock
Read Enable
Output Enable
Programmable
Read Controls
Empty Flag/
Output Ready
18-Bit Data Out Bus
Full Flag/
Input Ready
R
R
9
9
Figure 2. Multiple FIFO memory
with programmable flags used in depth expansion configuration
G
9.2 Depth Expansion
The depth expansion of AL4CS211/221/231/241/251 is also possible. The existence of two enable
pins on the read and write port allow depth expansion. The Write Enable 2<Load> pin is used as a
second write enable in a depth expansion configuration thus the programmable flags are set to the
default values. Depth expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A typical application
would have the expansion logic alternate data access from one device to the next in a sequential
manner. These FIFOs operate in the Depth Expansion configuration when the following conditions
are met:
相關(guān)PDF資料
PDF描述
AL4CS251 (512 x9. 1k x9. 2k x9. 4k x9. 8k x9) Synchronous FIFO
ALA110-SERIES ASIC
ALA201 ASIC
ALA202 ASIC
ALA300 ASIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AL4CS245 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
AL4CS251 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous FIFO
AL4CX263 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:16K/32K/64K/128K x9, 8K/16K/32K/64K x18 Synchronous FIFO
AL4CX273 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:16K/32K/64K/128K x9, 8K/16K/32K/64K x18 Synchronous FIFO
AL4CX283 制造商:AVERLOGIC 制造商全稱:AVERLOGIC 功能描述:16K/32K/64K/128K x9, 8K/16K/32K/64K x18 Synchronous FIFO
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*