參數(shù)資料
型號(hào)： AL422
英文描述： Single-Phase High Efficiency DC/DC Controller with On-Chip Gate Drivers for Intel Mobile CPUs
中文描述： 3M公司位FIFO的領(lǐng)域內(nèi)存
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 251K
代理商： AL422
AL422
AL422B
January 23, 2001
14
memory does not accept data input. The write address pointer is stopped at the current position. /WE
signal is fetched at the rising edge of the WCK cycle.
/RE Read Enable Input:
/RE controls the operation of the data output. When /RE is pulled low,
output data is provided at the rising edge of the RCK cycle and the internal read address is
incremented automatically. /RE signal is fetched at the rising edge of the RCK cycle.
/OE Output Enable Input: /
OE controls the enabling/disabling of the data output. When /OE is
pulled low, output data is provided at the rising edge of the RCK cycle. When /OE is pulled high, data
output is disabled and the output pins remain at high impedance status. /OE signal is fetched at the
rising edge of RCK cycle.
/WRST Write Reset Input:
This reset signal initializes the write address to 0, and is fetched at the
rising edge of the WCK input cycle.
/RRST Write Reset Input:
This reset signal initializes the read address to 0, and is fetched at the
rising edge of the RCK input cycle.
TST Test Pin:
For testing purpose only. It should be pulled low for normal applications.
DEC:
Decoupling cap pin, should be connected to a 1
μ
F or 2.2
μ
F capacitor to ground for 5V
application. For 3.3V application, the DEC pin can be simply connected to the 3.3V power with
regular 0.1
μ
F bypass capacitor.
8.1 Memory Operation
Initialization
Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal
operation.
Reset Operation
The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they
still need to meet the setup time and hold time requirements with reference to the clock input. When
the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are
enabled again. When /WRST signal is pulled low, the data input address will be set to 0 and the data
in the Input Buffer will be flushed into memory cell array. When /RRST signal is pulled low, the data
output address will be set to 0 and pre-fetch the data from memory cell array to Output Buffer.
相關(guān)PDF資料
PDF描述
AL4CS211 2-Phase, High Efficiency DC/DC Controller with On-Chip Gate Drivers for Intel Mobile CPUs
AL4CS221 2-Phase, High Efficiency DC/DC Controller with On-Chip Gate Drivers for Intel Mobile CPUs
AL4CS231 (512 x9. 1k x9. 2k x9. 4k x9. 8k x9) Synchronous FIFO
AL4CS241 (512 x9. 1k x9. 2k x9. 4k x9. 8k x9) Synchronous FIFO
AL4CS251 (512 x9. 1k x9. 2k x9. 4k x9. 8k x9) Synchronous FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AL422B 制造商:Averlogic Technologies 功能描述:
AL422V3 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:AL422 3M-Bits FIFO Field Memory
AL422V5 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:AL422 3M-Bits FIFO Field Memory
AL-425-244 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:HENKEL 功能描述:THERMOSTRATE HEATSINK PAD. 4.25"L X 2.44"W
AL42RT 制造商:ADAPTAFLEX 功能描述:TOOL ATS REMOVAL 42MM
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