參數(shù)資料
型號(hào)： AL2007LA
英文描述： Synchronous Push-Pull PWM Controllers; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +125°C
中文描述： AL2007LA為20MHz?170MHz的FSPLL AL2007LA |數(shù)據(jù)資料
文件頁(yè)數(shù)： 1/16頁(yè)
文件大?。?/td> 156K
代理商： AL2007LA
The AL2005H is a Phase-Locked Loop (PLL) frequency synthesizer
constructed in CMOS on single monolithic structure. The PLL Mac-
rofunctions provide frequency multiplication capabilities. The output
frequency Fout is related to the reference input clock frequency Fin
by the following equation:
Fout = ( m*Fin ) / ( p*s)
Where,
Fout is the output clock frequency.
Fin is the reference input clock frequency.
m,p and s are the values for programmable dividers.
AL2005H consists of a Phase/FrequencyDetector(PFD), a Charge
Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO),
a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as
shown in Figure1.
0.5
§-
CMOS Process Technology
5 Volt Single Power Supply
Output frequency Range: 20~ 170 MHz
Jitter
250ps
Input Duty Ratio 40% to 60%
Output Duty Ratio 40% to 60%
Frequency Changed by Programmable Divider
Power Down Mode
General Description
Features
FUNCTIONAL BLOCK DIAGRAM
Fin
Pre Divider
P
Charge
Pump
PFD
VCO
Main Divider
M
Post Scaler
S
Loop Filter
(External)
Fout
Figure 1. Phase Lockd Loop Block Diagram
20MHz ~ 170MHz FSPLL
AL2005H
SAMSUNG ELECTRONICS Co. LTD
DECEMBER 1998. Ver1.0
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