
DESCRIPTION
The Accutek AK591024 high density memory modules is a random
access memory organized in 1 Meg x 9 bit words. The assembly
consists of two 1 Meg x 4 and one 1 Meg x 1 DRAMs in surface
mountpackagesmountedonthefrontsideofaprintedcircuitboard.
Themodulecanbeconfiguredasaleadless30padSIMoraleaded
30 pin SIP. This packaging approach provides a better than 6 to 1
density increase over standard DIP packaging.
TheoperationoftheAK591024isidenticaltotwo1Megx4plusone
1 Meg x 1 DRAMs. For the lower eight bits, the data input is tied to
data output and brought out separately for each 1 Meg x 4 device,
with common RAS, CAS and WE control. The OE pins are tied to
Vss which dictates the use of early-write cycles to prevent conten-
tionofDandQ. SincetheWrite-Enable(WE)signalmustalwaysgo
lowbeforeCASinawritecycle,Read-WriteandRead-Modify-Write
operation is not possible. For the ninth bit, the data input (D
9)
and
dataoutput(Q
9
)pinsarebroughtoutseparatelyandcontrolledbya
separate PCAS for that bit. Bit nine is generally used for parity.
FEATURES
1,048,576 x 9 bit organization
Optional 30 Pad SIM (Single In-Line Module) or 30 Pin leaded
SIP (Single In-Line Package)
JEDEC standard pinout
Common CAS, RAS and WE control for the lower eight bits
1024 refresh cycles/16ms
Separate PCAS control for D
9
and Q
9
Power:
1.650 Watt Max Active (60 nS)
1.485 Watt Max Active (70 nS)
1.265 Watt Max Active (80 nS)
23.5 mWatt Standby (max)
Operating free air temperature: 0
o
to 70
o
C
Upward compatible with and AK594096 and AK5916384
Downward compaitble with AK59256
Functionally and Pin compatible with AK491024
Accutek
Microcircuit
Corporation
AK591024AS / AK591024AG
1,048,576 Word X 9 bit, CMOS
Dynamic Random Access Memory
1
30
+
+
1
+
+
Front View
30-Pin SIM
30-Pin SIP
PIN NOMENCLATURE
DQ
1
- DQ
8
Data In / Data Out
D
9
Data In
Q
9
Data Out
A
0
- A
9
Address Inputs
CAS, PCAS
Column Address Strobe
RAS
Row Address Strobe
WE
Write Enable
Vcc
5v Supply
Vss
Ground
NC
No Connect
MODULE OPTIONS
Leadless SIM: AK591024ASP
Leaded SIP: AK591024AGP
PIN ASSIGNMENT
PIN #
SYMBOL
PIN #
SYMBOL
1
Vcc
16
DQ5
2
CAS
17
A8
3
DQ1
18
A9
4
A0
19
NC
5
A1
20
DQ6
6
DQ2
21
WE
7
A2
22
Vss
8
A3
23
DQ7
9
Vss
24
NC
10
DQ3
25
DQ8
11
A4
26
Q9
12
A5
27
RAS
13
DQ4
28
PCAS
14
A6
29
D9
15
A7
30
Vcc
FUNCTIONAL DIAGRAM
*
A - A
RAS
CAS
WE
DQ1
DQ2
DQ3
DQ4
9
OE
*
*
*
A - A
RAS
CAS
WE
DQ1
DQ2
DQ3
DQ4
9
OE
*
*
*
A - A
RAS
CAS
WE
D
9
Q
*
*
*
+
+
+
+
+
WE
DQ1
DQ2
DQ3
DQ4
+
+
CAS
RAS
A - A
9
+
*
*
*
*
*
*
*
*
+
+
+
+
*
+
*
+
DQ5
DQ6
DQ7
DQ8
D9
Q9
*
+
PCAS
10