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參數(shù)資料
| 型號(hào)： | AIC812-46PVTR |
| 廠商： | Analog Integrations Corporation |
| 英文描述： | Reset Circuits with Manual Reset Input |
| 中文描述： | 復(fù)位電路，帶有手動(dòng)復(fù)位輸入 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 421K |
| 代理商： | AIC812-46PVTR |
AIC811/AIC812
MANUAL RESET INPUT
Many
μ
P-based products require manual reset
capability, allowing operators, test technicians, or
external logic circuitry to initiate a reset. Logic low
on
MR
asserts reset. Reset will remain asserted
for the Reset Active Timeout Period (t
RP
) after
MR
returns high. This input has an internal 20K
Ω
pull-up resistor, so it can be floating if it is not used.
MR
can be driven with TTL or CMOS-logic levels,
or with open-drain/collector outputs. Another
alternative is to connect a normal switch from
MR
to GND to create a manual reset function.
Connecting a 0.1μF capacitor from
MR
to ground
can provide noise immunity to prevent noise caused
by long cables of
MR
or noisy environment.
BENEFITS OF HIGHLY ACCURATE RESET
THRESHOLD
AIC811/812 with specified voltage as 5V
±
10% or
3V
±
10% are ideal for systems using a 5V
±
5% or 3V
±
5% power supply. The reset is guaranteed to
assert after the power supply falls out of regulation,
but before power drops below the minimum
specified operating voltage range of the system ICs.
The pre-trimmed thresholds are reducing the range
over which an undesirable reset may occur.
APPLICATION INFORMATION
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the
μ
P during
power-up, power-down, and brownout conditions,
AIC811
series
are
relatively
short-duration negative-going VCC transient.
resistant
to
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, AIC811
RESET
output no longer sinks current; it becomes an open
circuit. In this case, high-impedance CMOS logic
inputs connecting to
RESET
can drift to
undetermined voltages. Therefore, AIC811/2 with
CMOS is perfect for most applications of VCC
below 0.9V. However in applications where
RESET
must be valid down to 0V, adding a
pull-down resistor to
RESET
causes any leakage
currents to flow to ground, holding
RESET
low.
INTERFACING TO
μ
P WITH BIDIRECTIONAL
RESET PINS
μ
Ps with bidirectional reset pins can contend with
AIC811/812 reset outputs. If AIC811
RESET
output is asserted high and the
μ
P wants to pull it
low, indeterminate logic levels may occur. To
correct such cases, connect a resistor between
AIC811
RESET
(or AIC812 RESET) output and
the
μ
P reset I/O. Buffer the reset output to other
system components.
7
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