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參數(shù)資料
| 型號： | AIC812-44CVBG |
| 廠商： | Analog Integrations Corporation |
| 英文描述： | Reset Circuits with Manual Reset Input |
| 中文描述： | 復(fù)位電路，帶有手動復(fù)位輸入 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 421K |
| 代理商： | AIC812-44CVBG |
AIC811/AIC812
BLOCK DIAGRAM
6
R
PULL_UP
20K
R2
R1
MR
GND
RESET
(RESET)
Reset Generator
-
+
Bandgap
VCC
PIN DESCRIPTIONS
GND Pin
RESET
Pin (AIC811) : Active low output pin.
RESET
Output remains low while Vcc below reset
threshold.
RESET Pin (AIC812) : Active high output pin. RESET output remains high while Vcc below reset
threshold.
MR
Pin
: Logic low manual reset input. This active-low input has an internal 20k
pull-up
resistor. It can be driven by a TTL or CMOS, or shorted to ground with a switch.
Leave open when unused.
Vcc Pin
: Supply voltage.
DETAILED DESCRIPTIONS OF TECHNICAL TERMS
: Ground.
If a brownout condition occurs (VCC drops below
the reset threshold),
RESET
goes low. Any time
VCC goes below the reset threshold, the internal
timer resets to zero, and
RESET
goes low. The
internal timer is activated after VCC returns
above the reset threshold, and
RESET
remains
low for the reset timeout period.
The manual reset input (
MR
) can also initiate a
reset. AIC812 has an active-high RESET output
that is the inverse of AIC811’s
RESET
output.
RESET OUTPUT
μ
P will be activated at a valid reset state. These
μ
P supervisory circuits assert reset to prevent
code
execution
errors
power-down, or brownout conditions.
RESET
is guaranteed to be a logic low for
V
TH
>VCC>0.9V. Once VCC exceeds the reset
threshold, an internal timer keeps
RESET
low
for the reset timeout period; after this interval,
RESET
goes high.
during
power-up,
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