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參數(shù)資料
| 型號(hào)： | AIC2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 375K |
| 代理商： | AIC2 |
1
Features
Compatible with an Embedded ARM7TDMI
Processor
8-level Priority
From 2 to 32 Interrupt Sources
Individually Maskable and Vectored
Substantially Reduces the Software and Real-time Overhead in Handling Internal and
External Interrupts
Fast Forcing Feature Available
Includes Protect Mode Feature Via a Configuration Register
Can be Directly Connected to the Atmel Implementation of the AMBA
Peripheral Bus
(APB)
Fully Scan Testable (up to 99%)
Description
The Advanced Interrupt Controller 2 (AIC2) is an 8-level priority, individually maskable,
vectored interrupt controller. It can substantially reduce the software and real-time
overhead in handling internal and external interrupts.
This peripheral can be used with any 32-bit microcontroller core if the timing diagram
shown on page 4 is respected. The interrupt handling must be performed as
described on page 7, using the corresponding assembler instructions for the 32-bit
core used.
When using an ARM7TDMI
as the core, the Atmel bridge must be used to provide
the correct bus interface to the AIC2.
The interrupt controller can be directly connected to the nFIQ (fast interrupt request)
and the nIRQ (standard interrupt request) inputs of an ARM7TDMI processor, or the
equivalent inputs of another 32-bit microcontroller core. The fast forcing feature avail-
able in the AIC2 allows redirection of any internal or external interrupt source to
provide a fast interrupt rather than a normal interrupt. The processor’s nFIQ line can
be asserted either by the external fast interrupt request input FIQ, or by the other inter-
rupt sources via the fast forcing feature. The nIRQ line is asserted by all other interrupt
sources except those that assert FIQ.
An 8-level priority encoder allows the customer to define the priority between the dif-
ferent nIRQ interrupt sources. Internal interrupt sources are programmed to be level
sensitive or edge triggered. External interrupt sources can be programmed to be posi-
tive-edge or negative-edge triggered or high-level or low-level sensitive.
This document describes the AIC2 in a specific configuration as specified below:
One FIQ is connected on the interrupt line[0].
Eight internal interrupt sources are connected on interrupt lines[8:1].
Three external interrupt sources are connected on interrupt lines[11:9] but are
mapped on interrupts[18:16].
The interrupt sources are listed in Table 2 and the AIC2 programmable registers in
Table 3. The register interaction is shown in Figure 5.
32-bit
EmbeddedASIC
Core Peripheral
Advanced
Interrupt
Controller 2
(AIC2)
Rev. 1796B–CASIC–03/02
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