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參數(shù)資料
| 型號： | AHV2812DF/HBPBF |
| 元件分類： | 電源模塊 |
| 英文描述： | 2-OUTPUT 15 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | FM-10 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 179K |
| 代理商： | AHV2812DF/HBPBF |
www.irf.com
5
AHV28XX Series
Notes to Specifications (Triple Output Models)
Specifications (Triple Output Models) - continued
1. Tested at each output.
2. Parameter guaranteed by line and load regulation tests.
3. At least 25% of the total power should be taken from the (+5V) main output.
4. Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.
5. An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit
protection and is the condition of maximum power dissipation.
6. Capacitive load may be any value from 0 to the maximum limit without affecting dc performance. A capacitive load in excess of the
maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a
short circuit during turn-on.
7. Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be
guaranteed to the limits specified.
8. Above 125
°C case temperature, derate output power linearly to 0 at 135°C case.
9. Load step transition time between 2s and 10s.
10. Recovery time is measured from the initiation of the transient to where V
OUT has returned to within ±1% of VOUT at 50% load.
11. Input step transition time between 2s and 10s.
12. Turn on delay time measurement is for either a step application of power at input or the removal of a ground signal from the inhibit
pin (pin 8) while power is applied to the input.
Notes to Specifications (Dual Output Models)
1. Tested at each output.
2. Parameter guaranteed by line and load regulation tests.
3. Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.
4. Total power at both outputs.
5. When operating with unbalanced loads, at least 25% of the load must be on the positive output to maintain regulation.
6. Capacitive load may be any value from 0 to the maximum limit without affecting dc performance. A capacitive load in excess of the
maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a
short circuit during turn-on.
7. Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be
guaranteed to the limits specified.
8. An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit
protection and is the condition of maximum power dissipation.
9. Load step transition time between 2s and 10s.
10. Recovery time is measured from the initiation of the transient to where V
OUT has returned to within ±1% of VOUT at 50% load.
11. Input step transition time between 2s and 10s.
12. Turn on delay time measurement is for either a step application of power at input or the removal of a ground signal from the inhibit
pin (pin 2) while power is applied to the input.
13. Above 125
°C case temperature, derate output power linearly to 0 at 135°C.
AHV2812T
AHV2815T
TEST
SYMBOL
Condition
-55
°C ≤ TC ≤ +125°C,
VIN = 28 VDC ±5%, CL=0,
unless otherwise specified
Group A
Subgroups
Min
Max
Min
Max
Units
DYNAMIC
CHARACTERISTICS
Step Load Changes
Output Transient
9
Recovery
9,10
VOTLOAD
TTLOAD
50% Load 135 100% Load
No Load 135 50%
50% Load 135 100%
No Load 335 50% Load
50% Load 335 No lLoad
4
-300
-400
+300
+400
100
2000
5.0
-300
-400
+300
+400
100
2000
5.0
mVpk
s
ms
Step Line Changes
Output Transient
Recovery
7,10, 11
VOTLINE
TTLINE
Input step 16 to 40 VDC
Input step 40 to 16 VDC
Input step 16 to 40 VDC
Input step 40 to 16 VDC
4
1200
-1500
4.0
1200
-1500
4.0
mVpk
s
TURN-ON
Overshoot 1
Delay
1,12
VTonOS
T on D
IOUT = o and
±625mA
IOUT = o and ±625mA
4
750
15
750
15
mVpk
ms
Load Fault Recovery
7
TRLF
4
15
ms
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