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1997
3-203
AH-27
Micrel
3
Typical LDO Regulator
V
REF
V
OUT
C
0.33μF
R1
300k
R2
100k
V
ADJ
OUT
IN
GND
C
22μF
ADJ
MIC29153
V
IN
C
22μF
D1, D2 = 1N4148
D2
D1
Figure 3. Improved Slow Turn-On Circuit
2. Improved Simple Approach
Figure 3 is an improvement on the circuit of Figure 1 in that
it addresses the problems of potential instability and recov-
ery time. Diode D1 is added to the circuit to decouple the
(charged) capacitor from the feedback network, thereby
eliminating the effect of C
T
on the closed-loop transfer
function. Because of the non-linear effect of D1 being in
series with C
T
, there is a slightly longer “tail” associated with
approaching the final output voltage at turn-on. In the event
of a momentarily shorted output, diode D2 provides a low-
impedance discharge path for C
T
and thus assures the
desired turn-on behavior upon recovery.
Figure 4 shows the waveforms of the circuit of Figure 3. Note
that the initial step-function output is now 0.6V higher than
with the circuit of Figure 1. This approximately 1.8V turn-on
pedestal may be objectionable, especially in applications
where the output voltage is relatively low by design.
0
0
2
0.2
4
0.4
0.6
0.8
10
5
1.0
0
O
TIME (s)
Figure 4. Turn-On Behavior of Figure 3
3. Eliminating Initial Start-Up Pedestal
The circuits of Figures 1 and 3 depend upon the existence of
an output voltage (to create V
ADJ
) and, therefore, produce the
initial step-function voltage pedestals of about 1.2V and 1.8V,
as can be seen in Figures 2 and 4, respectively. The approach
of Figure 5 facilitates placing the output voltage origin at zero
volts because V
CONTROL
is derived from the input voltage. No
reactive component is added to the feedback circuit. The
value of R
T
should be considerably smaller than R3 to assure
that the junction of R
T
and C
T
acts like a voltage source
driving R3 and so R
T
is the primary timing control. If sufficient
current is introduced into the loop summing junction (via R3)
to generate V
ADJ
≥
V
REF
, then V
OUT
will be zero volts. As R
T
charges C
T
the voltage V
CONTROL
decays, which would
eventually result in V
ADJ
< V
REF
. However, since in normal
operation V
ADJ
= V
REF
, V
OUT
will become greater than zero
volts. The process continues until V
CONTROL
decays to
V
REF
+0.6V and V
OUT
reaches the desired value. This circuit
requires a regulator with an enable function, (e.g., the
MIC29152) because a small (< 2V) spike is generated coin-
cident with application of a step-function input voltage. Ca-
pacitor C1 and resistor R4 provide a short hold-off timing
function that eliminates this spike.
Figure 6 illustrates the timing of this operation. The small
initial delay (about 40 milliseconds) is the time interval during
which V
ADJ
> V
REF
. Since V
IN
is usually fairly consistent in
value R3 may be chosen to minimize this delay. Note that if
R3 is calculated based on the minimum foreseen V
IN
(as
described below), then higher values of V
IN
will produce
additional delay before the turn-on ramp begins. Conversely,
if V
IN (max)
is used for the calculation of R3, then lower values
of V
IN
will not produce the desired turn-on characteristic;
instead, there will be a small initial step-function prior to the
desired turn-on ramp. Recovery from a momentarily shorted
output is not addressed by this circuit, but interrupted input
voltage is handled properly. Notice that the build-up of
regulator output voltage differs from the waveforms of Fig-
ures 2 and 4 in that it is more ramp-like . This is because only
an initial portion of the RC charge waveform is used; i.e., while
V
CONTROL
> V
REF
+0.6V. The actual time constant used for
Figure 5 is 0.33 second, so 3
τ
is one second. As shown by
Figure 6, this provides about 600 milliseconds of ramp time,